SPMCK16Z4MPV20 datasheet(261/500 Pages) FREESCALE

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M68HC16 Z SERIES

MULTICHANNEL COMMUNICATION INTERFACE

USER’S MANUAL

10-21

A receive time clock is used to control sampling and synchronization. Data is shifted

into the receive serial shifter according to the most recent synchronization of the re-

ceive time clock with the incoming data stream. From this point on, data movement is

synchronized with the MCU system clock.

The number of bits shifted in by the receiver depends on the serial format. However,

all frames must end with at least one stop bit. When the stop bit is received, the frame

is considered to be complete, and the received data in the serial shifter is transferred

to the RDR. The receiver data register flag (RDRF) is set when the data is transferred.

Noise errors, parity errors, and framing errors can be detected while a data stream is

being received. Although error conditions are detected as bits are received, the noise

flag (NF), the parity flag (PF), and the framing error flag (FE) in SCSR are not set until

data is transferred from the serial shifter to the RDR.

RDRF must be cleared before the next transfer from the shifter can take place. If

RDRF is set when the shifter is full, transfers are inhibited and the overrun error (OR)

flag in SCSR is set. OR indicates that the RDR needs to be serviced faster. When OR

is set, the data in the RDR is preserved, but the data in the serial shifter is lost. Be-

cause framing, noise, and parity errors are detected while data is in the serial shifter,

FE, NF, and PF cannot occur at the same time as OR.

When the CPU16 reads SCSR and SCDR in sequence, it acquires status and data,

and also clears the status flags. Reading SCSR acquires status and arms the clearing

mechanism. Reading SCDR acquires data and clears SCSR.

When RIE in SCCR1 is set, an interrupt request is generated whenever RDRF is set.

Because receiver status flags are set at the same time as RDRF, they do not have

separate interrupt enables.

10.4.5.7 Idle-Line Detection

During a typical serial transmission, frames are transmitted isochronally and no idle

time occurs between frames. Even when all the data bits in a frame are logic ones, the

start bit provides one logic zero bit-time during the frame. An idle line is a sequence of

contiguous ones equal to the current frame size. Frame size is determined by the state

of the M bit in SCCR1.

The SCI receiver has both short and long idle-line detection capability. Idle-line detec-

tion is always enabled. The idle line type (ILT) bit in SCCR1 determines which type of

detection is used. When an idle line condition is detected, the IDLE flag in SCSR is set.

For short idle-line detection, the receiver bit processor counts contiguous logic one bit-

times whenever they occur. Short detection provides the earliest possible recognition

of an idle line condition, because the stop bit and contiguous logic ones before and

after it are counted. For long idle-line detection, the receiver counts logic ones after

the stop bit is received. Only a complete idle frame causes the IDLE flag to be set.

Freescale Semiconductor, Inc.

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