SPMCK16Z4MPV20 datasheet(260/500 Pages) FREESCALE

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MULTICHANNEL COMMUNICATION INTERFACE

M68HC16 Z SERIES

10-20

USER’S MANUAL

The state of the serial shifter is checked when the TE bit is set. If TC = 1, an idle frame

is transmitted as a preamble to the following data frame. If TC = 0, the current opera-

tion continues until the final bit in the frame is sent, then the preamble is transmitted.

The TC bit is set at the end of preamble transmission.

The SBK bit in SCCR1 is used to insert break frames in a transmission. A non-zero

integer number of break frames is transmitted while SBK is set. Break transmission

begins when SBK is set, and ends with the transmission in progress at the time either

SBK or TE is cleared. If SBK is set while a transmission is in progress, that transmis-

sion finishes normally before the break begins. To assure the minimum break time,

toggle SBK quickly to one and back to zero. The TC bit is set at the end of break trans-

mission. After break transmission, at least one bit-time of logic level one (mark idle) is

transmitted to ensure that a subsequent start bit can be detected.

If TE remains set, after all pending idle, data and break frames are shifted out, TDRE

and TC are set and TXD is held at logic level one (mark).

When TE is cleared, the transmitter is disabled after all pending idle, data, and break

frames are transmitted. The TC flag is set, and control of the TXD pin reverts to MPAR

and MDDR. Buffered data is not transmitted after TE is cleared. To avoid losing data

in the buffer, do not clear TE until TDRE is set.

Some serial communication systems require a mark on the TXD pin even when the

transmitter is disabled. Configure the TXD pin as an output, then write a one to PQS7.

When the transmitter releases control of the TXD pin, it reverts to driving a logic one

output.

To insert a delimiter between two messages, to place non-listening receivers in wake-

up mode between transmissions, or to signal a retransmission by forcing an idle line,

clear and then set TE before data in the serial shifter has shifted out. The transmitter

finishes the transmission, then sends a preamble. After the preamble is transmitted, if

TDRE is set, the transmitter will mark idle. Otherwise, normal transmission of the next

sequence will begin.

Both TDRE and TC have associated interrupts. The interrupts are enabled by the

transmit interrupt enable (TIE) and transmission complete interrupt enable (TCIE) bits

in SCCR1. Service routines can load the last byte of data in a sequence into SCDR,

then terminate the transmission when a TDRE interrupt occurs.

10.4.5.6 Receiver Operation

The RE bit in SCCR1 enables (RE = 1) and disables (RE = 0) the receiver. The receiv-

er contains a receive serial shifter and a parallel receive data register (RDR) located

in the SCI data register (SCDR). The serial shifter cannot be directly accessed by the

CPU16. The receiver is double-buffered, allowing data to be held in the RDR while oth-

er data is shifted in.

Receiver bit processor logic drives a state machine that determines the logic level for

each bit-time. This state machine controls when the bit processor logic is to sample

the RXD pin and also controls when data is to be passed to the receive serial shifter.

Freescale Semiconductor, Inc.

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