SPMCK16Z4MPV20 datasheet(259/500 Pages) FREESCALE

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M68HC16 Z SERIES

MULTICHANNEL COMMUNICATION INTERFACE

USER’S MANUAL

10-19

10.4.5.4 Parity Checking

The PT bit in SCCR1 selects either even (PT = 0) or odd (PT = 1) parity. PT affects

received and transmitted data. The PE bit in SCCR1 determines whether parity check-

ing is enabled (PE = 1) or disabled (PE = 0). When PE is set, the MSB of data in a

frame is used for the parity function. For transmitted data, a parity bit is generated for

received data; the parity bit is checked. When parity checking is enabled, the PF bit in

the SCI status register (SCSR) is set if a parity error is detected.

Enabling parity affects the number of data bits in a frame, which can in turn affect

frame size. Table 10-7 shows possible data and parity formats.

10.4.5.5 Transmitter Operation

The transmitter consists of a serial shifter and a parallel data register (TDR) located in

the SCI data register (SCDR). The serial shifter cannot be directly accessed by the

CPU16. The transmitter is double-buffered, which means that data can be loaded into

the TDR while other data is shifted out. The TE bit in SCCR1 enables (TE = 1) and

disables (TE = 0) the transmitter.

Shifter output is connected to the TXD pin while the transmitter is operating (TE = 1,

or TE = 0 and transmission in progress). Wired-OR operation should be specified

when more than one transmitter is used on the same SCI bus. The WOMS bit in

SCCR1 determines whether TXD is an open-drain (wired-OR) output or a normal

CMOS output. An external pull-up resistor on TXD is necessary for wired-OR opera-

tion. WOMS controls TXD function whether the pin is used by the SCI or as a general-

purpose I/O pin.

Data to be transmitted is written to SCDR, then transferred to the serial shifter. The

transmit data register empty (TDRE) flag in SCSR shows the status of TDR. When

TDRE = 0, the TDR contains data that has not been transferred to the shifter. Writing

to SCDR again overwrites the data. TDRE is set when the data in the TDR is trans-

ferred to the shifter. Before new data can be written to the SCDR, however, the pro-

cessor must clear TDRE by writing to SCSR. If new data is written to the SCDR without

first clearing TDRE, the data will not be transmitted.

The transmission complete (TC) flag in SCSR shows transmitter shifter state. When

TC = 0, the shifter is busy. TC is set when all shifting operations are completed. TC is

not automatically cleared. The processor must clear it by first reading SCSR while TC

is set, then writing new data to SCDR.

Table 10-7 Effect of Parity Checking on Data Size

Result

8 data bits

7 data bits, 1 parity bit

9 data bits

8 data bits, 1 parity bit

Freescale Semiconductor, Inc.

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