SPMCK16Z4MPV20 datasheet(272/500 Pages) FREESCALE

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GENERAL-PURPOSE TIMER

M68HC16 Z SERIES

11-8

USER’S MANUAL

11.5.5 Pulse-Width Modulation

Pulse-width modulation (PWMA/B) pins carry pulse-width modulator outputs. The

modulators can be programmed to generate a periodic waveform of variable frequen-

cy and duty cycle. PWMA can be used to output the clock selected as the input to the

PWM counter. These pins can also be used for general-purpose output. Refer to 11.11

Pulse-Width Modulation Unit for more information.

11.5.6 Auxiliary Timer Clock Input

The auxiliary timer clock input (PCLK) pin connects an external clock to the GPT. The

external clock can be used as the clock source for the capture/compare unit or the

PWM unit in place of one of the prescaler outputs. PCLK has hysteresis. Any pulse

longer than two system clocks is guaranteed to be valid and any pulse shorter than

one system clock is ignored. This pin can also be used as a general-purpose input pin.

Refer to 11.7 Prescaler for more information.

11.6 General-Purpose I/O

Any GPT pin can be used for general-purpose I/O when it is not used for another pur-

pose. Capture/compare pins are bidirectional, others can be used only for output or

input. I/O direction is controlled by a data direction bit in the port GP data direction reg-

ister (DDRGP).

Parallel data is read from and written to the port GP data register (PORTGP). Pin data

can be read even when pins are configured for a timer function. Data read from PORT-

GP always reflects the state of the external pin, while data written to PORTGP may

not always affect the external pin.

Data written to PORTGP does not immediately affect pins used for output compare

functions, but the data is latched. When an output compare function is disabled, the

last data written to PORTGP is driven out on the associated pin if it is configured as

an output. Data written to PORTGP can cause input captures if the corresponding pin

is configured for input capture function.

The pulse accumulator input (PAI) and the external clock input (PCLK) pins provide

general-purpose input. The state of these pins can be read by accessing the PAIS and

PCLKS bits in the pulse accumulator control register (PACTL).

Pulse-width modulation A and B (PWMA/B) output pins can serve as general-purpose

outputs. The force PWM value (FPWMx) and the force logic one (F1x) bits in the com-

pare force (CFORC) and PWM control (PWMC) registers, respectively, control their

operation.

11.7 Prescaler

Capture/compare and PWM units have independent 16-bit free-running counters as a

main timing component. These counters derive their clocks from the prescaler or from

the PCLK input. Figure 11-2 is a prescaler block diagram.

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SPMCK16Z4MPV20 Datasheet(PDF) 272 Page - Freescale Semiconductor, Inc

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