SPMCK16Z4MPV20 datasheet(269/500 Pages) FREESCALE

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M68HC16 Z SERIES

GENERAL-PURPOSE TIMER

USER’S MANUAL

11-5

For each bit in TFLG1 and TFLG2 there is a corresponding bit in TMSK1 and TMSK2

in the same bit position. If a mask bit is set and an associated event occurs, a hard-

ware interrupt request is generated.

In order to re-enable a status flag after an event occurs, the status flags must be

cleared. Status registers are cleared in a particular sequence. The register must first

be read for set flags, then zeros must be written to the flags that are to be cleared. If

a new event occurs between the time that the register is read and the time that it is

written, the associated flag is not cleared.

11.4.2 GPT Interrupts

The GPT has 11 internal sources that can cause it to request interrupt service (refer

to Table 11-2). Setting bits in TMSK1 and TMSK2 enables specific interrupt sources.

TMSK1 and TMSK2 are 8-bit registers that can be addressed individually or as one

16-bit register. The registers are initialized to zero at reset. For each bit in TMSK1 and

TMSK2 there is a corresponding bit in TFLG1 and TFLG2 in the same bit position.

TMSK2 also controls the operation of the timer prescaler. Refer to 11.7 Prescaler for

more information.

The value of the interrupt priority level (IPL[2:0]) field in the interrupt control register

(ICR) determines the priority of GPT interrupt requests. IPL[2:0] values correspond to

MCU interrupt request signals IRQ[7:1]. IRQ7 is the highest priority interrupt request

signal; IRQ1 is the lowest-priority signal. A value of %111 causes IRQ7 to be asserted

when a GPT interrupt request is made; lower field values cause corresponding lower-

priority interrupt request signals to be asserted. Setting field value to %000 disables

interrupts.

Table 11-1 GPT Status Flags

Flag

Mnemonic

Assignment

Source

IC1F

TFLG1

Input capture 1

IC2F

TFLG1

Input capture 2

IC3F

TFLG1

Input capture 3

OC1F

TFLG1

Output compare 1

OC2F

TFLG1

Output compare 2

OC3F

TFLG1

Output compare 3

OC4F

TFLG1

Output compare 4

I4/O5F

TFLG1

Input capture 4/output compare 5

TOF

TFLG2

Timer overflow

PAOVF

TFLG2

Pulse accumulator overflow

PAIF

TFLG2

Pulse accumulator input

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