 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
SPMCK16Z4MPV20 Datasheet(PDF) 305 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
SPMCK16Z4MPV20 Datasheet(HTML) 305 Page - Freescale Semiconductor, Inc |
|
|
305 / 500 page  M68HC16 Z SERIES ELECTRICAL CHARACTERISTICS USER’S MANUAL A-21 Table A-16 16.78-MHz AC Timing (V DD and V DDSYN = 5.0 Vdc ± 10 %, V SS = 0 Vdc, T A = T L to T H) 1 Num Characteristic Symbol Min Max Unit F1 Frequency of Operation f — 16.78 MHz 1 Clock Period tcyc 59.6 — ns 1A ECLK Period tEcyc 476 — ns 1B External Clock Input Period2 tXcyc 59.6 — ns 2, 3 Clock Pulse Width3 tCW 24 — ns 2A, 3A ECLK Pulse Width tECW 236 — ns 2B, 3B External Clock Input High/Low Time2 tXCHL 29.8 — ns 4, 5 CLKOUT Rise and Fall Time tCrf —5 ns 4A, 5A Rise and Fall Time (All Outputs except CLKOUT) trf —8 ns 4B, 5B External Clock Input Rise and Fall Time3 tXCrf —5 ns 6 Clock High to ADDR, FC, SIZE Valid4 tCHAV 029 ns 7 Clock High to ADDR, Data, FC, SIZE, High Impedance tCHAZx 059 ns 8 Clock High to ADDR, FC, SIZE, Invalid tCHAZn 0— ns 9 Clock Low to AS, DS, CS Asserted4 tCLSA 224 ns 9A AS to DS or CS Asserted (Read)5 tSTSA -15 15 ns 11 ADDR, FC, SIZE Valid to AS, CS, (and DS Read) Asserted tAVSA 15 — ns 12 Clock Low to AS, DS, CS Negated tCLSN 229 ns 13 AS, DS, CS Negated to ADDR, FC SIZE Invalid (Address Hold) tSNAI 15 — ns 14 AS, CS (and DS Read) Width Asserted tSWA 100 — ns 14A DS, CS Width Asserted (Write) tSWAW 45 — ns 14B AS, CS (and DS Read) Width Asserted (Fast Cycle) tSWDW 40 — ns 15 AS, DS, CS Width Negated6 tSN 40 — ns 16 Clock High to AS, DS, R/W High Impedance tCHSZ —59 ns 17 AS, DS, CS Negated to R/W High tSNRN 15 — ns 18 Clock High to R/W High tCHRH 029 ns 20 Clock High to R/W Low tCHRL 029 ns 21 R/W High to AS, CS Asserted tRAAA 15 — ns 22 R/W Low to DS, CS Asserted (Write) tRASA 70 — ns 23 Clock High to Data Out Valid tCHDO —29 ns 24 Data Out Valid to Negating Edge of AS, CS (Fast Write Cycle) tDVASN 15 — ns 25 DS, CS Negated to Data Out Invalid (Data Out Hold) tSNDOI 15 — ns 26 Data Out Valid to DS, CS Asserted (Write) tDVSA 15 — ns 27 Data In Valid to Clock Low (Data Setup)4 tDICL 5— ns 27A Late BERR, HALT Asserted to Clock Low (Setup Time) tBELCL 20 — ns 28 AS, DS Negated to DSACK[1:0], BERR, HALT, AVEC Negated tSNDN 080 ns 29 DS, CS Negated to Data In Invalid (Data In Hold)7 tSNDI 0— ns 29A DS, CS Negated to Data In High Impedance7, 8 tSHDI —55 ns Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
