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SPMCK16Z4MPV20 Datasheet(PDF) 309 Page - Freescale Semiconductor, Inc |
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SPMCK16Z4MPV20 Datasheet(HTML) 309 Page - Freescale Semiconductor, Inc |
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309 / 500 page  M68HC16 Z SERIES ELECTRICAL CHARACTERISTICS USER’S MANUAL A-25 Table A-18 25.17-MHz AC Timing (V DD and V DDSYN = 5.0 Vdc ± 5%, V SS = 0 Vdc, T A = T L to T H) 1 Num Characteristic Symbol Min Max Unit F1 Frequency of Operation f — 25.166 MHz 1 Clock Period tcyc 39.7 — ns 1A ECLK Period tEcyc 318 — ns 1B External Clock Input Period2 tXcyc 39.7 — ns 2, 3 Clock Pulse Width3 tCW 15 — ns 2A, 3A ECLK Pulse Width tECW 155 — ns 2B, 3B External Clock Input High/Low Time2 tXCHL 19.8 — ns 4, 5 CLKOUT Rise and Fall Time tCrf —5 ns 4A, 5A Rise and Fall Time (All Outputs except CLKOUT) trf —8 ns 4B, 5B External Clock Input Rise and Fall Time3 tXCrf —4 ns 6 Clock High to ADDR, FC, SIZ Valid4 tCHAV 019 ns 7 Clock High to ADDR, Data, FC, SIZ, High Impedance tCHAZx 039 ns 8 Clock High to ADDR, FC, SIZ, Invalid tCHAZn 0— ns 9 Clock Low to AS, DS, CS Asserted4 tCLSA 219 ns 9A AS to DS or CS Asserted (Read)5 tSTSA –10 15 ns 11 ADDR, FC, SIZE Valid to AS, CS, (and DS Read) Asserted tAVSA 8— ns 12 Clock Low to AS, DS, CS Negated tCLSN 219 ns 13 AS, DS, CS Negated to ADDR, FC, SIZ Invalid (Address Hold) tSNAI 8— ns 14 AS, CS (and DS Read) Width Asserted tSWA 65 — ns 14A DS, CS Width Asserted (Write) tSWAW 25 — ns 14B AS, CS (and DS Read) Width Asserted (Fast Cycle) tSWDW 22 — ns 15 AS, DS, CS Width Negated6 tSN 22 — ns 16 Clock High to AS, DS, R/W High Impedance tCHSZ —39 ns 17 AS, DS, CS Negated to R/W High tSNRN 10 — ns 18 Clock High to R/W High tCHRH 019 ns 20 Clock High to R/W Low tCHRL 019 ns 21 R/W High to AS, CS Asserted tRAAA 10 — ns 22 R/W Low to DS, CS Asserted (Write) tRASA 40 — ns 23 Clock High to Data Out Valid tCHDO —19 ns 24 Data Out Valid to Negating Edge of AS, CS (Fast Write Cycle) tDVASN 7— ns 25 DS, CS Negated to Data Out Invalid (Data Out Hold) tSNDOI 5— ns 26 Data Out Valid to DS, CS Asserted (Write) tDVSA 8— ns 27 Data In Valid to Clock Low (Data Setup)4 tDICL 5— ns 27A Late BERR, HALT Asserted to Clock Low (Setup Time) tBELCL 10 — ns 28 AS, DS Negated to DSACK[1:0], BERR, HALT, AVEC Negated tSNDN 050 ns 29 DS, CS Negated to Data In Invalid (Data In Hold)7 tSNDI 0— ns 29A DS, CS Negated to Data In High Impedance7, 8 tSHDI —45 ns Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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