SPMCK16Z4MPV20 datasheet(311/500 Pages) FREESCALE

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M68HC16 Z SERIES

ELECTRICAL CHARACTERISTICS

USER’S MANUAL

A-27

3. Parameters for an external clock signal applied while the internal PLL is disabled (MODCLK pin held low dur-

ing reset) do not pertain to an external reference applied while the PLL is enabled (MODCLK pin held high

during reset). When the PLL is enabled, the clock synthesizer detects successive transitions of the reference

signal. If transitions occur within the correct clock period, rise/fall times and duty cycle are not critical.

4. Address access time = (2.5 + WS) tcyc – tCHAV – tDICL

Chip select access time = (2 + WS) tcyc – tCLSA – tDICL

Where: WS = number of wait states. When fast termination is used (2 clock bus) WS = –1.

5. Specification 9A is the worst-case skew between AS and DS or CS. The amount of skew depends on the

relative loading of these signals. When loads are kept within specified limits, skew will not cause AS and DS

to fall outside the limits shown in specification 9.

6. If multiple-chip selects are used, CS width negated (specification 15) applies to the time from the negation of

a heavily loaded chip-select to the assertion of a lightly loaded chip select. The CS width negated specification

between multiple chip-selects does not apply to chip selects being used for synchronous ECLK cycles.

7. Hold times are specified with respect to DS or CS on asynchronous reads and with respect to CLKOUT on

fast cycle reads. The user is free to use either hold time.

8. Maximum value is equal to (tcyc / 2) + 25 ns.

9. If the asynchronous setup time (specification 47A) requirements are satisfied, the DSACK[1:0] low to data

setup time (specification 31) and DSACK[1:0] low to BERR low setup time (specification 48) can be ignored.

The data must only satisfy the data-in to clock low setup time (specification 27) for the following clock cycle.

BERR must satisfy only the late BERR low to clock low setup time (specification 27A) for the following clock

cycle.

10. To ensure coherency during every operand transfer, BG is not asserted in response to BR until after all cycles

of the current operand transfer are complete.

11. In the absence of DSACK[1:0], BERR is an asynchronous input using the asynchronous setup time (specifi-

cation 47A).

12. After external RESET negation is detected, a short transition period (approximately 2 tcyc) elapses, then the

SIM drives RESET low for 512 tcyc.

13. External logic must pull RESET high during this period in order for normal MCU operation to begin.

14. Eight pipeline states are multiplexed into IPIPE[1:0]. The multiplexed signals have two phases.

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SPMCK16Z4MPV20 Datasheet(PDF) 311 Page - Freescale Semiconductor, Inc