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SPMCK16Z4MPV20 Datasheet(PDF) 307 Page - Freescale Semiconductor, Inc |
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SPMCK16Z4MPV20 Datasheet(HTML) 307 Page - Freescale Semiconductor, Inc |
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307 / 500 page  M68HC16 Z SERIES ELECTRICAL CHARACTERISTICS USER’S MANUAL A-23 Table A-17 20.97-MHz AC Timing (V DD and V DDSYN = 5.0 Vdc ± 5%, V SS = 0 Vdc, T A = T L to T H) 1 Num Characteristic Symbol Min Max Unit F1 Frequency of Operation f — 20.97 MHz 1 Clock Period tcyc 47.7 — ns 1A ECLK Period tEcyc 381 — ns 1B External Clock Input Period2 tXcyc 47.7 — ns 2, 3 Clock Pulse Width3 tCW 18.8 — ns 2A, 3A ECLK Pulse Width tECW 183 — ns 2B, 3B External Clock Input High/Low Time2 tXCHL 23.8 — ns 4, 5 CLKOUT Rise and Fall Time tCrf —5 ns 4A, 5A Rise and Fall Time (All Outputs except CLKOUT) trf —8 ns 4B, 5B External Clock Input Rise and Fall Time3 tXCrf —5 ns 6 Clock High to ADDR, FC, SIZE Valid4 tCHAV 023 ns 7 Clock High to ADDR, Data, FC, SIZE, High Impedance tCHAZx 047 ns 8 Clock High to ADDR, FC, SIZE, Invalid tCHAZn 0— ns 9 Clock Low to AS, DS, CS Asserted4 tCLSA 023 ns 9A AS to DS or CS Asserted (Read)5 tSTSA -10 10 ns 11 ADDR, FC, SIZE Valid to AS, CS, (and DS Read) Asserted tAVSA 10 — ns 12 Clock Low to AS, DS, CS Negated tCLSN 223 ns 13 AS, DS, CS Negated to ADDR, FC SIZE Invalid (Address Hold) tSNAI 10 — ns 14 AS, CS (and DS Read) Width Asserted tSWA 80 — ns 14A DS, CS Width Asserted (Write) tSWAW 36 — ns 14B AS, CS (and DS Read) Width Asserted (Fast Cycle) tSWDW 32 — ns 15 AS, DS, CS Width Negated6 tSN 32 — ns 16 Clock High to AS, DS, R/W High Impedance tCHSZ —47 ns 17 AS, DS, CS Negated to R/W High tSNRN 10 — ns 18 Clock High to R/W High tCHRH 023 ns 20 Clock High to R/W Low tCHRL 023 ns 21 R/W High to AS, CS Asserted tRAAA 10 — ns 22 R/W Low to DS, CS Asserted (Write) tRASA 54 — ns 23 Clock High to Data Out Valid tCHDO —23 ns 24 Data Out Valid to Negating Edge of AS, CS (Fast Write Cycle) tDVASN 10 — ns 25 DS, CS Negated to Data Out Invalid (Data Out Hold) tSNDOI 10 — ns 26 Data Out Valid to DS, CS Asserted (Write) tDVSA 10 — ns 27 Data In Valid to Clock Low (Data Setup)4 tDICL 5— ns 27A Late BERR, HALT Asserted to Clock Low (Setup Time) tBELCL 15 — ns 28 AS, DS Negated to DSACK[1:0], BERR, HALT, AVEC Negated tSNDN 060 ns 29 DS, CS Negated to Data In Invalid (Data In Hold)7 tSNDI 0— ns 29A DS, CS Negated to Data In High Impedance7, 8 tSHDI —48 ns Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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