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SPMCK16Z4MPV20 Datasheet(PDF) 310 Page - Freescale Semiconductor, Inc |
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SPMCK16Z4MPV20 Datasheet(HTML) 310 Page - Freescale Semiconductor, Inc |
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310 / 500 page  ELECTRICAL CHARACTERISTICS M68HC16 Z SERIES A-26 USER’S MANUAL 30 CLKOUT Low to Data In Invalid (Fast Cycle Hold)7 tCLDI 8— ns 30A CLKOUT Low to Data In High Impedance7 tCLDH —60 ns 31 DSACK[1:0] Asserted to Data In Valid9 tDADI —35 ns 33 Clock Low to BG Asserted/Negated tCLBAN —19 ns 35 BR Asserted to BG Asserted10 tBRAGA 1— tcyc 37 BGACK Asserted to BG Negated tGAGN 12 tcyc 39 BG Width Negated tGH 2— tcyc 39A BG Width Asserted tGA 1— tcyc 46 R/W Width Asserted (Write or Read) tRWA 90 — ns 46A R/W Width Asserted (Fast Write or Read Cycle) tRWAS 55 — ns 47A Asynchronous Input Setup Time BR, BGACK, DSACK[1:0], BERR, AVEC, HALT tAIST 5— ns 47B Asynchronous Input Hold Time tAIHT 10 — ns 48 DSACK[1:0] Asserted to BERR, HALT Asserted11 tDABA —27 ns 53 Data Out Hold from Clock High tDOCH 0— ns 54 Clock High to Data Out High Impedance tCHDH —23 ns 55 R/W Asserted to Data Bus Impedance Change tRADC 25 — ns 70 Clock Low to Data Bus Driven (Show Cycle) tSCLDD 019 ns 71 Data Setup Time to Clock Low (Show Cycle) tSCLDS 8— ns 72 Data Hold from Clock Low (Show Cycle) tSCLDH 8— ns 73 BKPT Input Setup Time tBKST 10 — ns 74 BKPT Input Hold Time tBKHT 10 — ns 75 Mode Select Setup Time (DATA[15:0], MODCLK, BKPT) tMSS 20 — tcyc 76 Mode Select Hold Time (DATA[15:0], MODCLK, BKPT) tMSH 0— ns 77 RESET Assertion Time12 tRSTA 4— tcyc 78 RESET Rise Time13 tRSTR —10 tcyc 100 CLKOUT High to Phase 1 Asserted14 tCHP1A 334 ns 101 CLKOUT High to Phase 2 Asserted14 tCHP2A 334 ns 102 Phase 1 Valid to AS or DS Asserted14 tP1VSA 9— ns 103 Phase 2 Valid to AS or DS Asserted14 tP2VSN 9— ns 104 AS or DS Valid to Phase 1 Negated14 tSAP1N 9— ns 105 AS or DS Negated to Phase 2 Negated14 tSNP2N 9— ns NOTES: 1. All AC timing is shown with respect to VIH/VIL levels unless otherwise noted. 2. When an external clock is used, minimum high and low times are based on a 50% duty cycle. The minimum allowable tXcyc period is reduced when the duty cycle of the external clock varies. The relationship between external clock input duty cycle and minimum tXcyc is expressed: Minimum tXcyc period = minimum tXCHL / (50% – external clock input duty cycle tolerance). Table A-18 25.17-MHz AC Timing (Continued) (V DD and V DDSYN = 5.0 Vdc ± 5%, V SS = 0 Vdc, T A = T L to T H) 1 Num Characteristic Symbol Min Max Unit Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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