SPMCK16Z4MPV20 datasheet(430/500 Pages) FREESCALE

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M68HC16 Z SERIES

D-56

USER’S MANUAL

D.7.4 MCCI Interrupt Vector Register

The MIVR determines which three vectors in the exception vector table are to be used for

MCCI interrupts. The SPI and both SCI interfaces have separate interrupt vectors adja-

cent to one another. When initializing the MCCI, program INTV[7:2] so that INTV[7:0] cor-

respond to three of the user-defined vectors ($40–$FF). INTV[1:0] are determined by the

serial interface causing the interrupt, and are set by the MCCI.

At reset, MIVR is initialized to $0F, which corresponds to the uninitialized interrupt vector

in the exception table.

INTV[7:2] — Interrupt Vector

INTV[7:2] are the six high-order bits of the three MCCI interrupt vectors for the MCCI,

as programmed by the user.

INTV[1:0] — Interrupt Vector Source

INTV[1:0] are the two low-order bits of the three interrupt vectors for the MCCI. They

are automatically set by the MCCI to indicate the source of the interrupt. Refer to Table

D-38.

Writes to INTV0 and INTV1 have no meaning or effect. Reads of INTV0 and INTV1

return a value of one.

D.7.5 SPI Interrupt Level Register

The ILSPI determines the priority level of interrupts requested by the SPI.

Bits [15:14] — Not Implemented

MIVR — MCCI Interrupt Vector Register

$YFFC05

ILSCI

INTV[7:2]

INTV[1:0]

RESET:

Table D-38 Interrupt Vector Sources

INTV[1:0]

Source of Interrupt

SCIA

SCIB

SPI

ILSPI — SPI Interrupt Level Register

$YFFC06

NOT USED

ILSPI[2:0]

NOT USED

RESET:

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