SPMCK16Z4MPV20 datasheet(431/500 Pages) FREESCALE

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M68HC16 Z SERIES

USER’S MANUAL

D-57

ILSPI[2:0] — Interrupt Level for SPI

ILSPI[2:0] determine the interrupt request levels of SPI interrupts. Program this field

to a value from $0 (interrupts disabled) through $7 (highest priority). If the interrupt-

request level programmed in this field matches the interrupt-request level pro-

grammed for one of the SCI interfaces and both request an interrupt simultaneously,

the SPI is given priority.

Bits [10:8] — Not Implemented

D.7.6 MCCI Pin Assignment Register

The MPAR determines which of the SPI pins, with the exception of the SCK pin, are

actually used by the SPI submodule, and which pins are available for general-purpose

I/O. The state of SCK is determined by the SPI enable bit in SPCR1. Clearing a bit in

MPAR assigns the corresponding pin to general-purpose I/O; setting a bit assigns the

pin to the SPI. Refer to Table D-39.

Bits [15:8], [7:4], 2 — Not Implemented

SPI pins designated by the MPAR as general-purpose I/O are controlled only by

MDDR and PORTMC. The SPI has no effect on these pins. The MPAR does not affect

the operation of the SCI submodule.

MPAR — MCCI Pin Assignment Register

$YFFC08

NOT USED

MPA3

NOT

USED

MPA1

MPA0

RESET:

Table D-39 MPAR Pin Assignments

MPAR Field

MPAR Bit

Pin Function

MPA0

PMC0

MISO

MPA1

PMC1

MOSI

—1

NOTES:

1. MPA[7:4], MPA2 are not implemented.

—

PMC2

SCK

MPA3

PMC3

—1

—

PMC4

RXDB

—1

—

PMC5

TXDB

—1

—

PMC6

RXDA

—1

—

PMC7

TXDA

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