SPMCK16Z4MPV20 datasheet(435/500 Pages) FREESCALE

435 / 500 page

M68HC16 Z SERIES

USER’S MANUAL

D-61

Bit 15 — Not Implemented

LOOPS — Loop Mode

0 = Normal SCI operation, no looping, feedback path disabled.

1 = Test SCI operation, looping, feedback path enabled.

The LOOPS bit in SCCR1 controls a feedback path on the data serial shifter. When

LOOPS is set, SCI transmitter output is fed back into the receive serial shifter. The

TXD pin is asserted (idle line). Both transmitter and receiver must be enabled prior to

entering loop mode.

WOMS — Wired-OR Mode for SCI Pins

0 = If configured as an output, TXD is a normal CMOS output.

1 = If configured as an output, TXD is an open-drain output.

ILT — Idle-Line Detect Type

0 = Short idle-line detect (start count on first one).

1 = Long idle-line detect (start count on first one after stop bit(s)).

PT — Parity Type

0 = Even parity

1 = Odd parity

PE — Parity Enable

0 = SCI parity disabled.

1 = SCI parity enabled.

M — Mode Select

0 = 10-bit SCI frame (1 start bit, 8 data bits, 1 stop bit)

1 = 11-bit SCI frame (1 start bit, 9 data bits, 1 stop bit)

WAKE — Wake-Up by Address Mark

0 = SCI receiver awakened by idle-line detection.

1 = SCI receiver awakened by address mark (last data bit set).

TIE — Transmit Interrupt Enable

0 = SCI TDRE interrupts disabled.

1 = SCI TDRE interrupts enabled.

TCIE — Transmit Complete Interrupt Enable

0 = SCI TC interrupts disabled.

1 = SCI TC interrupts enabled.

RIE — Receiver Interrupt Enable

0 = SCI RDRF and OR interrupts disabled.

1 = SCI RDRF and OR interrupts enabled.

ILIE — Idle-Line Interrupt Enable

0 = SCI IDLE interrupts disabled.

1 = SCI IDLE interrupts enabled.

Freescale Semiconductor, Inc.

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