SPMCK16Z4MPV20 datasheet(438/500 Pages) FREESCALE

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M68HC16 Z SERIES

D-64

USER’S MANUAL

D.7.13 SPI Control Register

The SPCR contains parameters for configuring the SPI. The register can be read or

written at any time.

SPIE — SPI Interrupt Enable

0 = SPI interrupts disabled.

1 = SPI interrupts enabled.

SPE — SPI Enable

0 = SPI is disabled.

1 = SPI is enabled.

WOMP — Wired-OR Mode for SPI Pins

0 = Outputs have normal CMOS drivers.

1 = Pins designated for output by MDDR have open-drain drivers, regardless of

whether the pins are used as SPI outputs or for general-purpose I/O, and re-

gardless of whether the SPI is enabled.

MSTR — Master/Slave Mode Select

0 = SPI is a slave device.

1 = SPI is system master.

CPOL — Clock Polarity

0 = The inactive state value of SCK is logic level zero.

1 = The inactive state value of SCK is logic level one.

CPOL is used to determine the inactive state of the serial clock (SCK). It is used with

CPHA to produce a desired clock/data relationship between master and slave devices.

CPHA — Clock Phase

0 = Data captured on the leading edge of SCK and changed on the trailing edge of

SCK.

1 = Data is changed on the leading edge of SCK and captured on the trailing edge

of SCK.

CPHA determines which edge of SCK causes data to change and which edge causes

data to be captured. CPHA is used with CPOL to produce a desired clock/data rela-

tionship between master and slave devices.

LSBF — Least Significant Bit First

0 = Serial data transfer starts with LSB.

1 = Serial data transfer starts with MSB.

SPCR — SPI Control Register

$YFFC38

SPIE

SPE

WOMP

MSTR

CPOL

CPHA

LSBF

SIZE

SPBR[7:0]

RESET:

Freescale Semiconductor, Inc.

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