SPMCK16Z4MPV20 datasheet(432/500 Pages) FREESCALE

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M68HC16 Z SERIES

D-58

USER’S MANUAL

D.7.7 MCCI Data Direction Register

MDDR determines whether pins configured for general-purpose I/O are inputs or out-

puts. MDDR affects both SPI function and I/O function. During reset, all MCCI pins are

configured as inputs. Table D-40 shows the effect of MDDR on MCCI pin function.

MDDR — MCCI Data Direction Register

$YFFC0A

NOT USED

DDR7

DDR6

DDR5

DDR4

DDR3

DDR2

DDR1

DDR0

RESET:

Table D-40 Effect of MDDR on MCCI Pin Function

MCCI Pin

Mode

MDDR Bit

Bit State

Pin Function

MISO

Master

DDR0

Serial data input to SPI

Disables data input

Slave

Disables data output

Serial data output from SPI

MOSI

Master

DDR1

Disables data output

Serial data output from SPI

Slave

Serial data input to SPI

Disables data input

SCK1

NOTES:

1. SCK is automatically assigned to the SPI whenever the SPI is enabled (when the SPE

bit in the SPCR1 is set).

Master

DDR2

—

Clock output from SPI

Slave

—

Clock input to SPI

Master

DDR3

Assertion causes mode fault

General-purpose I/O

Slave

SPI slave-select input

Disables slave-select input

RXDB2

2. PMC4 and PMC6 function as general-purpose I/O pins when the corresponding RE bit

in the SCI control register (SCCR0A or SCCR0B) is cleared.

—

DDR4

General-purpose I/O

Serial data input to SCIB

TXDB3

3. PMC5 and PMC7 function as general-purpose I/O pins when the corresponding TE bit

in the SCI control register (SCCR0A or SCCR0B) is cleared.

—

DDR5

General-purpose I/O

Serial data output from SCIB

RXDA

—

DDR6

General-purpose I/O

Serial data input to SCIA

TXDA3

—

DDR7

General-purpose I/O

Serial data output from SCIA

Freescale Semiconductor, Inc.

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