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SPMCK16Z4MPV20 Datasheet(PDF) 160 Page - Freescale Semiconductor, Inc |
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SPMCK16Z4MPV20 Datasheet(HTML) 160 Page - Freescale Semiconductor, Inc |
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160 / 500 page  SYSTEM INTEGRATION MODULE M68HC16 Z SERIES 5-54 USER’S MANUAL NOTE Pins that are not used should either be configured as outputs, or (if configured as inputs) pulled to the appropriate inactive state. This de- creases additional IDD caused by digital inputs floating near mid-sup- ply level. 5.7.5.1 Reset States of SIM Pins Generally, while RESET is asserted, SIM pins either go to an inactive high-impedance state or are driven to their inactive states. After RESET is released, mode selection occurs, and reset exception processing begins. Pins configured as inputs must be driven to the desired active state. Pull-up or pull-down circuitry may be necessary. Pins configured as outputs begin to function after RESET is released. Table 5-21 is a sum- mary of SIM pin states during reset. 5.7.5.2 Reset States of Pins Assigned to Other MCU Modules As a rule, module pins that are assigned to general-purpose I/O ports go into a high- impedance state following reset. However, during power-on reset, module port pins may be in an indeterminate state for a short period. Refer to 5.7.7 Power-On Reset for more information. Table 5-21 SIM Pin Reset States Pin(s) Pin State While RESET Asserted Pin State After RESET Released Default Function Alternate Function Pin Function Pin State Pin Function Pin State CS10/ADDR23/ECLK VDD CS10 VDD ADDR23 Unknown CS[9:6]/ADDR[22:19]/PC[6:3] VDD CS[9:6] VDD ADDR[22:19] Unknown ADDR[18:0] High-Z ADDR[18:0] Unknown ADDR[18:0] Unknown AS/PE5 High-Z AS Output PE5 Input AVEC/PE2 High-Z AVEC Input PE2 Input BERR High-Z BERR Input BERR Input CS1/BG VDD CS1 VDD BG VDD CS2/BGACK VDD CS2 VDD BGACK Input CS0/BR VDD CS0 VDD BR Input CLKOUT Output CLKOUT Output CLKOUT Output CSBOOT VDD CSBOOT VSS CSBOOT VSS DATA[15:0] Mode select DATA[15:0] Input DATA[15:0] Input DS/PE4 High-Z DS Output PE4 Input DSACK0/PE0 High-Z DSACK0 Input PE0 Input DSACK1/PE1 High-Z DSACK1 Input PE1 Input CS[5:3]/FC[2:0]/PC[2:0] VDD CS[5:3] VDD FC[2:0] Unknown HALT High-Z HALT Input HALT Input IRQ[7:1]/PF[7:1] High-Z IRQ[7:1] Input PF[7:1] Input MODCLK/PF0 Mode Select MODCLK Input PF0 Input R/W High-Z R/W Output R/W Output RESET Asserted RESET Input RESET Input SIZ[1:0]/PE[7:6] High-Z SIZ[1:0] Unknown PE[7:6] Input TSC Mode select TSC Input TSC Input Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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