SPMCK16Z4MPV20 datasheet(162/500 Pages) FREESCALE

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SYSTEM INTEGRATION MODULE

M68HC16 Z SERIES

5-56

USER’S MANUAL

The SIM clock synthesizer provides clock signals to the other MCU modules. After the

clock is running and MSTRST is asserted for at least four clock cycles, these modules

reset. VDD ramp time and VCO frequency ramp time determine how long the four cy-

cles take. Worst case is approximately 15 milliseconds. During this period, module

port pins may be in an indeterminate state. While input-only pins can be put in a known

state by external pull-up resistors, external logic on input/output or output-only pins

during this time must condition the lines. Active drivers require high-impedance buffers

or isolation resistors to prevent conflict.

Figure 5-20 is a timing diagram for power-on reset. It shows the relationships between

RESET, VDD, and bus signals.

Figure 5-20 Power-On Reset

5.7.8 Use of the Three-State Control Pin

Asserting the three-state control (TSC) input causes the MCU to put all output drivers

in a disabled, high-impedance state. The signal must remain asserted for approxi-

mately ten clock cycles in order for drivers to change state.

When the internal clock synthesizer is used (MODCLK held high during reset), synthe-

sizer ramp-up time affects how long the ten cycles take. Worst case is approximately

20 milliseconds from TSC assertion.

When an external clock signal is applied (MODCLK held low during reset), pins go to

high-impedance state as soon after TSC assertion as approximately ten clock pulses

have been applied to the EXTAL pin.

16 POR TIM

CLKOUT

VCO

LOCK

BUS

CYCLES

RESET

VDD

NOTES:

1. INTERNAL START-UP TIME

2. FIRST INSTRUCTION FETCHED

2 CLOCKS

512 CLOCKS

10 CLOCKS

ADDRESS AND

CONTROL SIGNALS

THREE-STATED

BUS STATE

UNKNOWN

Freescale Semiconductor, Inc.

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