SPMCK16Z4MPV20 datasheet(166/500 Pages) FREESCALE

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SYSTEM INTEGRATION MODULE

M68HC16 Z SERIES

5-60

USER’S MANUAL

Although arbitration is intended to deal with simultaneous requests of the same inter-

rupt level, it always takes place, even when a single source is requesting service. This

is important for two reasons: the EBI does not transfer the interrupt acknowledge read

cycle to the external bus unless the SIM wins contention, and failure to contend causes

the interrupt acknowledge bus cycle to be terminated early by a bus error.

When arbitration is complete, the module with both the highest asserted interrupt level

and the highest arbitration priority must terminate the bus cycle. Internal modules

place an interrupt vector number on the data bus and generate appropriate internal cy-

cle termination signals. In the case of an external interrupt request, after the interrupt

acknowledge cycle is transferred to the external bus, the appropriate external device

must respond with a vector number, then generate data size acknowledge (DSACK)

termination signals, or it must assert the autovector (AVEC) request signal. If the de-

vice does not respond in time, the SIM bus monitor, if enabled, asserts the bus error

signal (BERR), and a spurious interrupt exception is taken.

Chip-select logic can also be used to generate internal AVEC or DSACK signals in re-

sponse to interrupt acknowledgment cycles. Refer to 5.9.3 Using Chip-Select Sig-

nals for Interrupt Acknowledge for more information. Chip-select address match

logic functions only after the EBI transfers an interrupt acknowledge cycle to the exter-

nal bus following IARB contention. All interrupts from internal modules have their as-

sociated IACK cycles terminated with an internal DSACK. Thus, user vectors (instead

of autovectors) must always be used for interrupts generated from internal modules. If

an internal module makes an interrupt request of a certain priority, and the appropriate

chip-select registers are programmed to generate AVEC or DSACK signals in re-

sponse to an interrupt acknowledge cycle for that priority level, chip-select logic does

not respond to the interrupt acknowledge cycle, and the internal module supplies a

vector number and generates internal cycle termination signals.

For periodic timer interrupts, the PIRQ[2:0] field in the periodic interrupt control register

(PICR) determines PIT priority level. A PIRQ[2:0] value of %000 means that PIT inter-

rupts are inactive. By hardware convention, when the CPU16 receives simultaneous

interrupt requests of the same level from more than one SIM source (including external

devices), the periodic interrupt timer is given the highest priority, followed by the IRQ

pins.

5.8.4 Interrupt Processing Summary

A summary of the entire interrupt processing sequence follows. When the sequence

begins, a valid interrupt service request has been detected and is pending.

A. The CPU16 finishes higher priority exception processing or reaches an instruc-

tion boundary.

B. Processor state is stacked, then the CCR PK extension field is cleared.

C. The interrupt acknowledge cycle begins:

1. FC[2:0] are driven to %111 (CPU space) encoding.

2. The address bus is driven as follows. ADDR[23:20] = %1111; ADDR[19:16]

= %1111, which indicates that the cycle is an interrupt acknowledge CPU

space cycle; ADDR[15:4] = %111111111111; ADDR[3:1] = the priority of

the interrupt request being acknowledged; and ADDR0 = %1.

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SPMCK16Z4MPV20 Datasheet(PDF) 166 Page - Freescale Semiconductor, Inc

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