SPMCK16Z4MPV20 datasheet(165/500 Pages) FREESCALE

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M68HC16 Z SERIES

SYSTEM INTEGRATION MODULE

USER’S MANUAL

5-59

Interrupt requests are sampled on consecutive falling edges of the system clock. In-

terrupt request input circuitry has hysteresis. To be valid, a request signal must be as-

serted for at least two consecutive clock periods. Valid requests do not cause

immediate exception processing, but are left pending. Pending requests are pro-

cessed at instruction boundaries or when exception processing of higher-priority inter-

rupts is complete.

The CPU16 does not latch the priority of a pending interrupt request. If an interrupt

source of higher priority makes a service request while a lower priority request is pend-

ing, the higher priority request is serviced. If an interrupt request with a priority equal

to or lower than the current IP mask value is made, the CPU16 does not recognize the

occurrence of the request. If simultaneous interrupt requests of different priorities are

made, and both have a priority greater than the mask value, the CPU16 recognizes

the higher-level request.

5.8.3 Interrupt Acknowledge and Arbitration

When the CPU16 detects one or more interrupt requests of a priority higher than the

interrupt priority mask value, it places the interrupt request level on the address bus

and initiates a CPU space read cycle. The request level serves two purposes: it is de-

coded by modules or external devices that have requested interrupt service, to deter-

mine whether the current interrupt acknowledge cycle pertains to them, and it is

latched into the interrupt priority mask field in the CPU16 condition code register to

preclude further interrupts of lower priority during interrupt service.

Modules or external devices that have requested interrupt service must decode the IP

mask value placed on the address bus during the interrupt acknowledge cycle and re-

spond if the priority of the service request corresponds to the mask value. However,

before modules or external devices respond, interrupt arbitration takes place.

Arbitration is performed by means of serial contention between values stored in indi-

vidual module interrupt arbitration (IARB) fields. Each module that can make an inter-

rupt service request, including the SIM, has an IARB field in its configuration register.

IARB fields can be assigned values from %0000 to %1111. In order to implement an

arbitration scheme, each module that can request interrupt service must be assigned

a unique, non-zero IARB field value during system initialization. Arbitration priorities

range from %0001 (lowest) to %1111 (highest). If the CPU16 recognizes an interrupt

service request from a source that has an IARB field value of %0000, a spurious inter-

rupt exception is processed.

WARNING

Do not assign the same arbitration priority to more than one module.

When two or more IARB fields have the same nonzero value, the

CPU16 interprets multiple vector numbers at the same time, with un-

predictable consequences.

Because the EBI manages external interrupt requests, the SIM IARB value is used for

arbitration between internal and external interrupt requests. The reset value of IARB

for the SIM is %1111, and the reset IARB value for all other modules is %0000.

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