SPMCK16Z4MPV20 datasheet(167/500 Pages) FREESCALE

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M68HC16 Z SERIES

SYSTEM INTEGRATION MODULE

USER’S MANUAL

5-61

3. Request priority is latched into the CCR IP field from the address bus.

D. Modules or external peripherals that have requested interrupt service decode

the priority value in ADDR[3:1]. If request priority is the same as acknowledged

priority, arbitration by IARB contention takes place.

E. After arbitration, the interrupt acknowledge cycle is completed in one of the fol-

lowing ways:

1. When there is no contention (IARB = %0000), the spurious interrupt monitor

asserts BERR, and the CPU16 generates the spurious interrupt vector

number.

2. The dominant interrupt source supplies a vector number and DSACK sig-

nals appropriate to the access. The CPU16 acquires the vector number.

3. The AVEC signal is asserted (the signal can be asserted by the dominant

interrupt source or the pin can be tied low), and the CPU16 generates an

autovector number corresponding to interrupt priority.

4. The bus monitor asserts BERR and the CPU16 generates the spurious in-

terrupt vector number.

F. The vector number is converted to a vector address.

G. The content of the vector address is loaded into the PC and the processor

transfers control to the exception handler routine.

5.8.5 Interrupt Acknowledge Bus Cycles

Interrupt acknowledge bus cycles are CPU space cycles that are generated during ex-

ception processing. For further information about the types of interrupt acknowledge

bus cycles determined by AVEC or DSACK, refer to APPENDIX A ELECTRICAL

CHARACTERISTICS and the

SIM Reference Manual (SIMRM/AD).

5.9 Chip-Selects

Typical microcontrollers require additional hardware to provide external chip-select

signals. The MCU includes 12 programmable chip-select circuits that can provide from

two to 16 clock-cycle access to external memory and peripherals. Address block sizes

of 2 Kbytes to 512 Kbytes can be selected. However, because ADDR[23:20] follow the

state of ADDR19, 512-Kbyte blocks are the largest usable size. Figure 5-21 is a dia-

gram of a basic system that uses chip-selects.

Freescale Semiconductor, Inc.

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