SPMCK16Z4MPV20 datasheet(164/500 Pages) FREESCALE

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SYSTEM INTEGRATION MODULE

M68HC16 Z SERIES

5-58

USER’S MANUAL

5.8 Interrupts

Interrupt recognition and servicing involve complex interaction between the SIM, the

CPU16, and a device or module requesting interrupt service. This discussion provides

an overview of the entire interrupt process. Chip-select logic can also be used to re-

spond to interrupt requests. Refer to 5.9 Chip-Selects for more information.

5.8.1 Interrupt Exception Processing

The CPU16 handles interrupts as a type of asynchronous exception. An exception is

an event that preempts normal processing. Exception processing makes the transition

from normal instruction execution to execution of a routine that deals with an excep-

tion. Each exception has an assigned vector that points to an associated handler rou-

tine. These vectors are stored in a vector table located in the first 512 bytes of address

bank 0. The CPU16 uses vector numbers to calculate displacement into the table. Re-

fer to 4.13 Exceptions for more information.

5.8.2 Interrupt Priority and Recognition

The CPU16 provides for seven levels of interrupt priority (1 – 7), seven automatic in-

terrupt vectors, and 200 assignable interrupt vectors. All interrupts with priorities less

than seven can be masked by the interrupt priority (IP) field in the condition code

There are seven interrupt request signals (IRQ[7:1]). These signals are used internally

on the IMB, and there are corresponding pins for external interrupt service requests.

The CPU16 treats all interrupt requests as though they come from internal modules;

external interrupt requests are treated as interrupt service requests from the SIM.

Each of the interrupt request signals corresponds to an interrupt priority level. IRQ1

has the lowest priority and IRQ7 the highest.

The IP field consists of three bits (CCR[7:5]). Binary values %000 to %111 provide

eight priority masks. Masks prevent an interrupt request of a priority less than or equal

to the mask value (except for IRQ7) from being recognized and processed. When IP

contains %000, no interrupt is masked. During exception processing, the IP field is set

to the priority of the interrupt being serviced.

Interrupt recognition is determined by interrupt priority level and interrupt priority (IP)

mask value. The interrupt priority mask consists of three bits in the CPU16 condition

code register (CCR[7:5]). Binary values %000 to %111 provide eight priority masks.

Masks prevent an interrupt request of a priority less than or equal to the mask value

from being recognized and processed. IRQ7, however, is always recognized, even if

the mask value is %111.

IRQ[7:1] are active-low level-sensitive inputs. The low on the pin must remain asserted

until an interrupt acknowledge cycle corresponding to that level is detected.

IRQ7 is transition-sensitive as well as level-sensitive: a level-7 interrupt is not detected

unless a falling edge transition is detected on the IRQ7 line. This prevents redundant

servicing and stack overflow. A non-maskable interrupt is generated each time IRQ7

is asserted as well as each time the priority mask is written while IRQ7 is asserted. If

IRQ7 is asserted and the IP mask is written to any new value (including %111), IRQ7

will be recognized as a new IRQ7.

Freescale Semiconductor, Inc.

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