SPMCK16Z4MPV20 datasheet(163/500 Pages) FREESCALE

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M68HC16 Z SERIES

SYSTEM INTEGRATION MODULE

USER’S MANUAL

5-57

NOTE

When TSC assertion takes effect, internal signals are forced to val-

ues that can cause inadvertent mode selection. Once the output driv-

ers change state, the MCU must be powered down and restarted

before normal operation can resume.

5.7.9 Reset Processing Summary

To prevent write cycles in progress from being corrupted, a reset is recognized at the

end of a bus cycle, and not at an instruction boundary. Any processing in progress at

the time a reset occurs is aborted. After SIM reset control logic has synchronized an

internal or external reset request, the MSTRST signal is asserted.

The following events take place when MSTRST is asserted.

A. Instruction execution is aborted.

B. The condition code register is initialized.

1. The IP field is set to $7, disabling all interrupts below priority 7.

2. The S bit is set, disabling LPSTOP mode.

3. The SM bit is cleared, disabling MAC saturation mode.

C. The K register is cleared.

NOTE

All CCR bits that are not initialized are not affected by reset. Howev-

er, out of power-on reset, these bits are indeterminate.

The following events take place when MSTRST is negated after assertion.

A. The CPU16 samples the BKPT input.

B. The CPU16 fetches RESET vectors in the following order:

1. Initial ZK, SK, and PK extension field values

2. Initial PC

3. Initial SP

4. Initial IZ value

Vectors can be fetched from internal RAM or from external ROM enabled by

the CSBOOT signal.

C. The CPU16 begins fetching instructions pointed to by the initial PK : PC.

5.7.10 Reset Status Register

The reset status register (RSR) contains a bit for each reset source in the MCU. When

a reset occurs, a bit corresponding to the reset type is set. When multiple causes of

reset occur at the same time, more than one bit in RSR may be set. The reset status

to APPENDIX D REGISTER SUMMARY.

Freescale Semiconductor, Inc.

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Go to: www.freescale.com

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