PIC18LF4331 datasheet(235/392 Pages) MICROCHIP

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 2010 Microchip Technology Inc.

DS39616D-page 235

PIC18F2331/2431/4331/4431

20.4.2

EUSART SYNCHRONOUS MASTER

RECEPTION

Once Synchronous mode is selected, reception is

enabled by setting either the Single Receive Enable bit,

SREN (RCSTA<5>), or the Continuous Receive

Enable bit, CREN (RCSTA<4>). Data is sampled on the

RC7/RX/DT/SDO pin on the falling edge of the clock.

If enable bit SREN is set, only a single word is received.

If enable bit CREN is set, the reception is continuous

until CREN is cleared. If both bits are set, then CREN

takes precedence.

To set up a Synchronous Master Reception:

Initialize the SPBRGH:SPBRG registers for the

appropriate baud rate. Set or clear the BRGH

and BRG16 bits, as required, to achieve the

desired baud rate.

Enable the synchronous master serial port by

setting bits, SYNC, SPEN and CSRC.

Ensure bits, CREN and SREN, are clear.

If interrupts are desired, set enable bit, RCIE.

If 9-bit reception is desired, set bit, RX9.

If a single reception is required, set bit, SREN.

For continuous reception, set bit, CREN.

Interrupt flag bit, RCIF, will be set when

reception is complete and an interrupt will be

generated if the enable bit, RCIE, was set.

Read the RCSTA register to get the 9th bit (if

enabled) and determine if any error occurred

during reception.

Read the 8-bit received data by reading the

RCREG register.

10. If any error occurred, clear the error by clearing

bit, CREN.

11. If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

FIGURE 20-12:

SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

CREN bit

RC7/RX/DT/SDO

RC6/TX/CK/SS

Write to

SREN bit

RCIF bit

(Interrupt)

Read

RXREG

Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

‘0’

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

‘0’

Q1 Q2 Q3 Q4

Note:

Timing diagram demonstrates Sync Master mode with SREN bit = 1 and BRGH bit = 0.

RC6/TX/CK/SS

(SCKP = 0)

(SCKP = 1)

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