PIC18LF4331 datasheet(62/392 Pages) MICROCHIP

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PIC18F2331/2431/4331/4431

DS39616D-page 62

 2010 Microchip Technology Inc.

6.1.1

PROGRAM COUNTER

The Program Counter (PC) specifies the address of the

instruction to fetch for execution. The PC is 21 bits wide

and contained in three 8-bit registers. The low byte,

known as the PCL register, is both readable and writ-

able. The high byte (PCH register) contains the

PC<15:8> bits and is not directly readable or writable.

Updates to the PCH register are performed through the

PCLATH register. The upper byte is the PCU register

and contains the bits, PC<20:16>. This register is also

not directly readable or writable. Updates to the PCU

The contents of PCLATH and PCLATU are transferred

to the program counter by any operation that writes to

the PCL. Similarly, the upper two bytes of the program

counter are transferred to PCLATH and PCLATU by an

operation that reads PCL. This is useful for computed

offsets to the PC (see Section 6.1.4.1 “Computed

GOTO”

The PC addresses bytes in the program memory. To

prevent the PC from becoming misaligned with word

instructions, the Least Significant bit of the PCL is fixed

to a value of ‘0‘. The PC increments by two to address

sequential instructions in the program memory.

The CALL, RCALL, GOTO and program branch instruc-

tions write to the program counter directly. For these

instructions, the contents of PCLATH and PCLATU are

not transferred to the program counter.

6.1.2

RETURN ADDRESS STACK

The return address stack allows any combination of up

to 31 program calls and interrupts to occur. The PC

(Program Counter) is pushed onto the stack when a

CALL

or RCALL instruction is executed, or an interrupt

is Acknowledged. The PC value is pulled off the stack

on a RETURN, RETLW or a RETFIE instruction.

PCLATU and PCLATH are not affected by any of the

RETURN

or CALL instructions.

The stack operates as a 31-word by 21-bit RAM and a

5-bit Stack Pointer, with the Stack Pointer initialized to

00000b after all Resets. There is no RAM associated

with Stack Pointer, 00000b. This is only a Reset value.

During a CALL type instruction, causing a push onto the

stack, the Stack Pointer is first incremented and the

RAM location pointed to by the Stack Pointer is written

with the contents of the PC (already pointing to the

instruction following the CALL). During a RETURN type

instruction, causing a pop from the stack, the contents

of the RAM location pointed to by the STKPTR are

transferred to the PC and then the Stack Pointer is

decremented.

The stack space is not part of either program or data

space. The Stack Pointer is readable and writable, and

the address on the top of the stack is readable and

writable through the Top-of-Stack (TOS) Special Function

Registers. Data can also be pushed to, or popped from,

the stack using the Top-of-Stack SFRs. Status bits

indicate if the stack is full, has overflowed or underflowed.

6.1.2.1

Top-of-Stack Access

The top of the stack is readable and writable. Three

contents of the stack location pointed to by the

STKPTR register (Figure 6-3). This allows users to

implement a software stack if necessary. After a CALL,

RCALL

or interrupt, the software can read the pushed

value by reading the TOSU, TOSH and TOSL registers.

These values can be placed on a user-defined software

stack. At return time, the software can replace the

TOSU, TOSH and TOSL and do a return.

The user must disable the global interrupt enable bits

while accessing the stack to prevent inadvertent stack

corruption.

6.1.2.2

Return Stack Pointer (STKPTR)

The STKPTR register (Register 6-1) contains the Stack

Pointer value, the STKFUL (Stack Full) status bit and

the STKUNF (Stack Underflow) status bits. The value

of the Stack Pointer can be 0 through 31. The Stack

Pointer increments before values are pushed onto the

stack and decrements after values are popped off the

stack. At Reset, the Stack Pointer value will be zero.

The user may read and write the Stack Pointer value.

This feature can be used by a Real-Time Operating

System (RTOS) for return stack maintenance.

After the PC is pushed onto the stack 31 times (without

popping any values off the stack), the STKFUL bit is

set. The STKFUL bit is cleared by software or by a

POR.

The action that takes place when the stack becomes

full depends on the state of the STVREN (Stack Over-

flow Reset Enable) Configuration bit. (Refer to

Section 23.1 “Configuration Bits”

for a description of

the device Configuration bits.) If STVREN is set

(default), the 31st push will push the (PC + 2) value

onto the stack, set the STKFUL bit and reset the

device. The STKFUL bit will remain set and the Stack

Pointer will be set to zero.

If STVREN is cleared, the STKFUL bit will be set on the

31st push and the Stack Pointer will increment to 31.

Any additional pushes will not overwrite the 31st push

and STKPTR will remain at 31.

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