PIC18LF4331 datasheet(82/392 Pages) MICROCHIP

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PIC18F2331/2431/4331/4431

DS39616D-page 82

 2010 Microchip Technology Inc.

7.7

Operation During Code-Protect

Data EEPROM memory has its own code-protect bits in

Configuration Words. External read and write opera-

tions are disabled if either of these mechanisms are

enabled.

The microcontroller itself can both read and write to the

internal data EEPROM, regardless of the state of the

code-protect Configuration bit. Refer to Section 23.0

“Special Features of the CPU”

for additional

information.

7.8

Protection Against Spurious Write

There are conditions when the device may not want to

write to the data EEPROM memory. To protect against

spurious EEPROM writes, various mechanisms have

been implemented. On power-up, the WREN bit is

cleared. In addition, writes to the EEPROM memory

are blocked during the Power-up Timer period (TPWRT,

Parameter 33).

The write/initiate sequence, and the WREN bit

together, help prevent an accidental write during

Brown-out Reset, power glitch or software malfunction.

7.9

Using the Data EEPROM

The data EEPROM is a high-endurance, byte-

addressable array that has been optimized for the

storage of frequently changing information (e.g.,

program variables or other data that are updated

often). Frequently changing values will typically be

updated more often than Specification D124. If this is

not the case, an array refresh must be performed. For

this reason, variables that change infrequently (such as

constants, IDs, calibration, etc.) should be stored in

Flash program memory.

A simple data EEPROM refresh routine is shown in

Example 7-3.

EXAMPLE 7-3:

DATA EEPROM REFRESH ROUTINE

Note:

If data EEPROM is only used to store con-

stants and/or data that changes rarely, an

array refresh is likely not required. See

Specification D124.

CLRF

EEADR

; Start at address 0

BCF

EECON1, CFGS

; Set for memory

BCF

EECON1, EEPGD

; Set for Data EEPROM

BCF

INTCON, GIE

; Disable interrupts

BSF

EECON1, WREN

; Enable writes

LOOP

; Loop to refresh array

BSF

EECON1, RD

; Read current address

MOVLW

55h

;

MOVWF

EECON2

; Write 55h

Required

MOVLW

0AAh

;

Sequence

MOVWF

EECON2

; Write 0AAh

BSF

EECON1, WR

; Set WR bit to begin write

BTFSC

EECON1, WR

; Wait for write to complete

BRA

$-2

INCFSZ

EEADR, F

; Increment address

BRA

LOOP

; Not zero, do it again

BCF

EECON1, WREN

; Disable writes

BSF

INTCON, GIE

; Enable interrupts

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