PIC18LF4331 datasheet(79/392 Pages) MICROCHIP

79 / 392 page

 2010 Microchip Technology Inc.

DS39616D-page 79

PIC18F2331/2431/4331/4431

7.0

DATA EEPROM MEMORY

The data EEPROM is readable and writable during

normal operation over the entire VDD range. The data

memory is not directly mapped in the register file

space. Instead, it is indirectly addressed through the

Special Function Registers (SFR).

There are four SFRs used to read and write the

program and data EEPROM memory. These registers

are:

• EECON1

• EECON2

• EEDATA

• EEADR

The EEPROM data memory allows byte read and write.

When interfacing to the data memory block, EEDATA

holds the 8-bit data for read/write and EEADR holds the

address of the EEPROM location being accessed.

These devices have 256 bytes of data EEPROM with

an address range from 00h to FFh.

The EEPROM data memory is rated for high erase/

write cycle endurance. A byte write automatically

erases the location and writes the new data (erase-

before-write). The write time is controlled by an on-chip

timer. The write time will vary with voltage and

temperature, as well as from chip-to-chip. Please

refer to Parameter D122 (Table 26-1 in Section 26.0

“Electrical Characteristics”

) for exact limits.

7.1

EEADR

The Address register can address 256 bytes of data

EEPROM.

7.2

EECON1 and EECON2 Registers

Access to the data EEPROM is controlled by two

registers: EECON1 and EECON2. These are the same

registers which control access to the program memory

and are used in a similar manner for the data

EEPROM.

The EECON1 register (Register 7-1) is the control

bit, EEPGD, determines if the access will be to program

or data EEPROM memory. When clear, operations will

access the data EEPROM memory. When set, program

memory is accessed.

Control bit, CFGS, determines if the access will be to

the Configuration registers or to program memory/data

EEPROM memory. When set, subsequent operations

access Configuration registers. When CFGS is clear,

the EEPGD bit selects either Flash program or data

EEPROM memory.

The WREN bit, when set, will allow a write operation.

On power-up, the WREN bit is clear. The WRERR bit is

set in hardware when the WREN bit is set and cleared

when the internal programming timer expires and the

write operation is complete.

The WR control bit initiates write operations. The bit

cannot be cleared, only set, in software; it is cleared in

hardware at the completion of the write operation.

Control bits, RD and WR, start read and erase/write

operations, respectively. These bits are set by firmware

and cleared by hardware at the completion of the

operation.

The RD bit cannot be set when accessing program

memory (EEPGD = 1). Program memory is read using

table read instructions. See Section 7.3 “Reading the

Data EEPROM Memory”

regarding table reads.

The EECON2 register is not a physical register. It is

used exclusively in the memory write and erase

sequences. Reading EECON2 will read all ‘0’s.

Note:

During normal operation, the WRERR bit

is read as ‘1’. This can indicate that a write

operation was prematurely terminated by

a Reset or a write operation was

attempted improperly.

Note:

The EEIF interrupt flag bit (PIR2<4>) is

set when the write is complete. It must be

cleared in software.

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