Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

PIC18LF4331 Datasheet(PDF) 53 Page - Microchip Technology

Part # PIC18LF4331
Description  28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D
PDF  392 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC18LF4331 Datasheet(HTML) 53 Page - Microchip Technology

Back Button PIC18LF4331 Datasheet HTML 49Page - Microchip Technology PIC18LF4331 Datasheet HTML 50Page - Microchip Technology PIC18LF4331 Datasheet HTML 51Page - Microchip Technology PIC18LF4331 Datasheet HTML 52Page - Microchip Technology PIC18LF4331 Datasheet HTML 53Page - Microchip Technology PIC18LF4331 Datasheet HTML 54Page - Microchip Technology PIC18LF4331 Datasheet HTML 55Page - Microchip Technology PIC18LF4331 Datasheet HTML 56Page - Microchip Technology PIC18LF4331 Datasheet HTML 57Page - Microchip Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 53 / 392 page
background image
 2010 Microchip Technology Inc.
DS39616D-page 53
PIC18F2331/2431/4331/4431
FIGURE 5-7:
TIME-OUT SEQUENCE ON POR w/PLL ENABLED (MCLR TIED TO VDD)
TABLE 5-2:
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Condition
Program
Counter
RCON
Register
RI
TO
PD
POR
BOR
STKFUL STKUNF
Power-on Reset
0000h
0--1 1100
1
1
1
0
0
0
0
RESET
Instruction
0000h
0--0 uuuu
0
u
u
u
u
u
u
Brown-out
0000h
0--1 11u-
1
1
1
u
0
u
u
MCLR Reset during power-managed
Run modes
0000h
0--u 1uuu
u
1
u
u
u
u
u
MCLR Reset during power-managed Idle
and Sleep modes
0000h
0--u 10uu
u
1
0
u
u
u
u
WDT Time-out during full power or
power-managed Run modes
0000h
0--u 0uuu
u
0
u
u
u
u
u
MCLR Reset during full-power execution
0000h
0--u uuuu
u
u
u
u
u
uu
Stack Full Reset (STVREN = 1)
1u
Stack Underflow Reset (STVREN = 1)
u1
Stack Underflow Error (not an actual
Reset, STVREN = 0)
0000h
u--u uuuu
u
u
u
u
u
u
1
WDT time-out during power-managed Idle
or Sleep modes
PC + 2
u--u 00uu
u
0
0
u
u
u
u
Interrupt exit from power-managed modes PC + 2(1) u--u u0uu
u
u
0
u
u
u
u
Legend:
u
= unchanged, x = unknown, - = unimplemented bit, read as ‘0’.
Note 1:
When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (0x000008h or 0x000018h).
TPWRT
TOST
VDD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
PLL TIME-OUT
TPLL
Note:
TOST = 1024 clock cycles.
TPLL
 2 ms max. First three stages of the PWRT timer.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com