PIC18LF4331 datasheet(65/392 Pages) MICROCHIP

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 2010 Microchip Technology Inc.

DS39616D-page 65

PIC18F2331/2431/4331/4431

6.1.4.2

Table Reads and Table Writes

A better method of storing data in program memory

allows two bytes of data to be stored in each instruction

location. Look-up table data may be stored, two bytes

per program word, by using table reads and writes.

The Table Pointer register (TBLPTR) specifies the byte

address and the Table Latch register (TABLAT) con-

tains the data that is read from or written to program

memory. Data is transferred to or from program

memory, one byte at a time.

Table read and table write operations are discussed

further in Section 8.1 “Table Reads and Table

Writes”

6.2

Clocking Scheme/Instruction

Cycle

The clock input (from OSC1) is internally divided by

four to generate four non-overlapping quadrature

clocks, namely Q1, Q2, Q3 and Q4. Internally, the

Program Counter (PC) is incremented every Q1, the

instruction is fetched from the program memory and

latched into the Instruction Register (IR) in Q4. The

instruction is decoded and executed during the

following Q1 through Q4. The clocks and instruction

execution flow are shown in Figure 6-4.

FIGURE 6-4:

CLOCK/INSTRUCTION CYCLE

6.3

Instruction Flow/Pipelining

An “Instruction Cycle” consists of four Q cycles (Q1,

Q2, Q3 and Q4). The instruction fetch and execute are

pipelined such that fetch takes one instruction cycle,

while decode and execute take another instruction

cycle. However, due to the pipelining, each instruction

effectively executes in one cycle. If an instruction

causes the program counter to change (e.g., GOTO),

then two cycles are required to complete the instruction

(Example 6-3).

A fetch cycle begins with the Program Counter (PC)

incrementing in Q1.

In the execution cycle, the fetched instruction is latched

into the “Instruction Register” (IR) in cycle, Q1. This

instruction is then decoded and executed during the

Q2, Q3 and Q4 cycles. Data memory is read during Q2

(operand read) and written during Q4 (destination

write).

EXAMPLE 6-3:

INSTRUCTION PIPELINE FLOW

OSC1

OSC2/CLKO

(RC mode)

PC + 2

PC + 4

Fetch INST (PC)

Execute INST (PC – 2)

Fetch INST (PC + 2)

Execute INST (PC)

Fetch INST (PC + 4)

Execute INST (PC + 2)

Internal

Phase

Clock

All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction

is “flushed” from the pipeline, while the new instruction is being fetched and then executed.

TCY0TCY1TCY2TCY3TCY4TCY5

1. MOVLW 55h

Fetch 1

Execute 1

2. MOVWF PORTB

Fetch 2

Execute 2

3. BRA SUB_1

Fetch 3

Execute 3

4. BSF

PORTA, BIT3 (Forced NOP)

Fetch 4

Flush (NOP)

5. Instruction @ address SUB_1

Fetch SUB_1 Execute SUB_1

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