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PIC18LF4331 Datasheet(PDF) 47 Page - Microchip Technology |
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PIC18LF4331 Datasheet(HTML) 47 Page - Microchip Technology |
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47 / 392 page ![]() 2010 Microchip Technology Inc. DS39616D-page 47 PIC18F2331/2431/4331/4431 5.0 RESET The PIC18F2331/2431/4331/4431 devices differentiate between various kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during Sleep d) Watchdog Timer (WDT) Reset (during execution) e) Programmable Brown-out Reset (BOR) f) RESET Instruction g) Stack Full Reset h) Stack Underflow Reset This section discusses Resets generated by MCLR, POR and BOR, and the operation of the various start- up timers. Stack Reset events are covered in Section 6.1.2.4 “Stack Full/Underflow Resets” . WDT Resets are covered in Section 23.2 “Watchdog Timer (WDT)” . A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 5-1. FIGURE 5-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT S R Q External Reset MCLR VDD OSC1 WDT Time-out VDD Rise Detect OST/PWRT INTRC POR Pulse OST 10-Bit Ripple Counter PWRT Chip_Reset 11-Bit Ripple Counter Enable OST(1) Enable PWRT Note 1: See Table 5-1 for time-out situations. Brown-out Reset BOREN RESET Instruction Stack Pointer Stack Full/Underflow Reset Sleep ( )_IDLE 1024 Cycles 65.5 ms 32 s MCLRE |
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