PIC18LF4331 datasheet(59/392 Pages) MICROCHIP

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 2010 Microchip Technology Inc.

DS39616D-page 59

PIC18F2331/2431/4331/4431

CAP3BUFL/

MAXCNTL

2331 2431 4331 4431

xxxx xxxx

uuuu uuuu

CAP1CON

2331 2431 4331 4431

-0-- 0000

-u-- uuuu

CAP2CON

2331 2431 4331 4431

-0-- 0000

-u-- uuuu

CAP3CON

2331 2431 4331 4431

-0-- 0000

-u-- uuuu

DFLTCON

2331 2431 4331 4431

-000 0000

-uuu uuuu

TABLE 5-3:

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Applicable Devices

Power-on Reset,

Brown-out Reset

MCLR Resets

WDT Reset

RESET

Instruction

Stack Resets

Wake-up via WDT

or Interrupt

Legend: u

= unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1:

One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the

interrupt vector (0008h or 0018h).

When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

See Table 5-2 for Reset value for specific condition.

Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read ‘0’.

Bit 3 of PORTE and LATE are enabled if MCLR functionality is disabled. When not enabled as the PORTE

pin, they are disabled and read as ‘0’. The 28-pin devices do not have only RE3 implemented.

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