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PIC18LF4331 Datasheet(PDF) 132 Page - Microchip Technology |
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PIC18LF4331 Datasheet(HTML) 132 Page - Microchip Technology |
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132 / 392 page  PIC18F2331/2431/4331/4431 DS39616D-page 132 2010 Microchip Technology Inc. 13.1 Timer1 Operation Timer1 can operate in one of these modes: •As a timer • As a synchronous counter • As an asynchronous counter The operating mode is determined by the Timer1 Clock Select bit, TMR1CS (T1CON<1>). When TMR1CS = 0, Timer1 increments every instruc- tion cycle. When TMR1CS = 1, Timer1 increments on every rising edge of the external clock input or the Timer1 oscillator, if enabled. When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI/CCP2/FLTA and RC0/T1OSO/ T1CKI pins become inputs. That is, the TRISC<1:0> value is ignored and the pins are read as ‘0’. Timer1 also has an internal “Reset input”. This Reset can be generated by the CCP module (see Section 16.4.4 “Special Event Trigger” ). FIGURE 13-1: TIMER1 BLOCK DIAGRAM FIGURE 13-2: TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE) T1SYNC TMR1CS T1CKPS<1:0> Sleep Input T1OSCEN(1) FOSC/4 Internal Clock On/Off Prescaler 1, 2, 4, 8 Synchronize Detect 1 0 2 T1OSO/T1CKI T1OSI 1 0 TMR1ON TMR1L Set TMR1IF on Overflow TMR1 High Byte Clear TMR1 (CCP Special Event Trigger) Timer1 Oscillator Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. On/Off Timer1 Timer1 Clock Input T1SYNC TMR1CS T1CKPS<1:0> Sleep Input T1OSCEN(1) FOSC/4 Internal Clock Prescaler 1, 2, 4, 8 Synchronize Detect 1 0 2 T1OSO/T1CKI T1OSI Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. 1 0 TMR1L Internal Data Bus 8 Set TMR1IF on Overflow TMR1 TMR1H High Byte 8 8 8 Read TMR1L Write TMR1L 8 TMR1ON Clear TMR1 (CCP Special Event Trigger) Timer1 Oscillator On/Off Timer1 Timer1 Clock Input |
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