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HT82B42R Datasheet(PDF) 56 Page - Holtek Semiconductor Inc |
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HT82B42R Datasheet(HTML) 56 Page - Holtek Semiconductor Inc |
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56 / 86 page ![]() Rev. 1.00 56 October 27, 2011 Rev. 1.00 57 October 27, 2011 HT82B42R/HT82B42RE I/O MCU with USB Interface TheMCUcancommunicatewiththeendpointFIFObysettingthecorrespondingregisters,of whichtheaddressislistedinthefollowingtable.Afterreadingthecurrentdata,thenextdatawill showafter2μs,thisisusedtochecktheendpointFIFOstatusandresponsetotheMISCregister,if read/writeactionisstillgoingon. Registers R/W Bank Address Bit7~Bit0 FIFO0 R/W 1 48H Data7~Data0 FIFO1 R/W 1 49H Data7~Data0 FIFO2 R/W 1 4AH Data7~Data0 Therearesometimingconstrainsandusagesillustratedhere.BysettingtheMISCregister,theMCU canperformreading,writingandclearingactions.Therearesomeexamplesshowninthefollowing tableforendpoinFIFOreading,writingandclearing. Actions MISC Setting Flow and Status Read FIFO0 sequence 00H→01H→delay 2μs, check 41H→read* from FIFO0 register and check not ready (01H) →03H→02H Write FIFO1 sequence 0AH→0BH→delay 2μs, check 4BH→write* to FIFO1 register and check not ready (0BH) →09H→08H Check whether FIFO0 can be read or not 00H→01H→delay 2μs, check 41H (read) or 01H (not ready) →00H Check whether FIFO1 can be written or not 0AH→0BH→delay 2μs, check 4BH (read) or 0BH (not ready) →0AH Read 0-sized packet sequence from FIFO0 00H→01H→delay 2μs, check 81H→read once (01H)→03H→S02H Write 0-sized packet sequence to FIFO1 0AH→0BH→delay 2μs, check 4BH→09H→08H Note:*:Thereisa2μstimebetween2readactionsorbetween2writeactions. |
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