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SM320DM6446 Datasheet(PDF) 71 Page - Texas Instruments |
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SM320DM6446 Datasheet(HTML) 71 Page - Texas Instruments |
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71 / 228 page  3.5.4 PINMUX0 Register Description 3.5.5 PINMUX1 Register Description SM320DM6446 Digital Media System-on-Chip www.ti.com SPRS607A – JUNE 2009 – REVISED JUNE 2009 The PINMUX0 pin multiplexing register controls which peripheral is given ownership over shared pins among EMAC, CCD, LCD, RGB888, RGB666, ATA, VLYNQ, EMIFA, HPI, and GPIO peripherals. The register format is shown in Figure 3-7 and bit field descriptions are given in Table 3-14. More details on the PINMUX0 pin muxing fields are given in Section 3.5.6. A value of '1' enables the secondary or tertiary pin function. Figure 3-7. PINMUX0 Register(1) 31 30 29 28 27 26 25 24 23 22 21 18 17 16 EMACEN Rsvd HPIEN Rsvd CFLDEN CWE LFLDEN LOEEN RGB888 RGB666 Reserved ATAEN HDIREN R/W-0 R/W-0 R/W-D R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0000 R/W-0 R/W-0 15 14 13 12 11 10 9 5 4 0 VLYNQEN VLSCREN VLYNQWD AECS5 AECS4 Reserved AEAW R/W-0 R/W-0 R/W-00 R/W-0 R/W-0 R-00000 R/W-LLLL LEGEND: R = Read; W = Write; L = pin state latched at reset rising edge; D = derived from pin states; -n = value after reset (1) For proper DM6446 device operation, always write a value of '0' to RSV bits 30 and 29 Table 3-14. PINMUX0 Register Description Name Description EMACEN Enable EMAC and MDIO function on default GPIO3V[0:16] pins. HPIEN Enable HPI module pins. Default value is derived from BTSEL[1:0] configuration inputs. HPIEN is 1 when the BTSEL[1:0] = 10 for non-secure devices only. HPIEN default state is always 0 for secure divices. CFLDEN Enable CCD C_FIELD function on default GPIO[4] pin CWE Enable CCD C_WE function on default GPIO[1] pin LFLDEN Enable LCD_FIELD function on default GPIO[3] pin LOEEN Enable LCD_OE function on default GPIO[0] pin RGB888 Enable VPBE RGB888 function on default GPIO[2:6, 46:47] pins RGB666 Enable VPBE RGB666 function on default GPIO[46:47] pins ATAEN Enable ATA function on default EMIFA and GPIO[52:53] pins and shared UART1 pins HDIREN Enable HDDIR function on default GPIO[42] pin VLYNQEN Enable VLYNQ function on default GPIO[9,10:17] pins VLSCREN Enable VLYNQ SCRUN function on default GPIO[9] pin VLYNQWD VLYNQ data width selection. This expands the VLYNQ TXD[0:3] and RXD[0:3] functions on default GPIO[10:17] pins. AECS5 Enable EMIFA EM_CS5 function on GPIO[8] AECS4 Enable EMIFA EM_CS4 function on GPIO[9] AEAW EMIFA address width selection. Default value is latched at reset from AEAW[4:0] configuration input pins. This enables EMIF address function on default GPIO[10:28] pins. The PINMUX1 pin multiplexing register controls which peripheral is given ownership over shared pins among Timer, PLL, ASP, SPI, I2C, PWM, and UART peripherals. The register format is shown in Figure 3-8 and bit field descriptions are given in Table 3-15. More details on the PINMUX1 pin muxing fields are given in Section 3.5.6. A value of "1" enables the secondary or tertiary pin function. Submit Documentation Feedback Device Configurations 71 |
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