SM320DM6446 datasheet(90/228 Pages) TI1

90 / 228 page

SM320DM6446

Digital Media System-on-Chip

SPRS607A – JUNE 2009 – REVISED JUNE 2009

www.ti.com

Table 6-3. DM6446 Power and Clock Domains

POWER DOMAIN

CLOCK DOMAIN

PERIPHERAL/MODULE

Always On

CLKIN

UART0

Always On

CLKIN

UART1

Always On

CLKIN

UART2

Always On

CLKIN

I2C

Always On

CLKIN

Timer0

Always On

CLKIN

Timer1

Always On

CLKIN

Timer2

Always On

CLKIN

PWM0

Always On

CLKIN

PWM1

Always On

CLKIN

PWM2

Always On

CLKDIV2

ARM Subsystem

Always On

CLKDIV3

DDR2

Always On

CLKDIV3

VPSS

Always On

CLKDIV3

EDMA

Always On

CLKDIV3

SCR

Always On

CLKDIV6

GPSC

Always On

CLKDIV6

LPSCs

Always On

CLKDIV6

Ice Pick

Always On

CLKDIV6

EMIFA

Always On

CLKDIV6

USB

Always On

CLKDIV6

HPI

Always On

CLKDIV6

VLYNQ

Always On

CLKDIV6

EMAC

Always On

CLKDIV6

ATA/CF

Always On

CLKDIV6

MMC/SD/SDIO

Always On

CLKDIV6

SPI

Always On

CLKDIV6

ASP

Always On

CLKDIV6

GPIO

DSP

CLKDIV1

C64x+ CPU

Table 6-4. DM6446 Clock Domains(1)

CLOCK MODES (FREQUENCY)

SUBSYSTEM

FIXED RATIO vs. PLL1

PLL BYPASS

PLL ENABLED

PLL1

–

27 MHz

594 MHz

DSP

1:1

27 MHz

594 MHz

ARM

1:2

13.5 MHz

297 MHz

EDMA3/VPSS

1:3

9 MHz

198 MHz

Peripherals

1:6

4.5 MHz

99 MHz

(1)

These table values assume a MXI/CLKIN of 27 MHz and a PLL1 multiplier equal to 22.

Peripheral and Electrical Specifications

Submit Documentation Feedback

SM320DM6446 Datasheet(PDF) 90 Page - Texas Instruments

SM320DM6446 Datasheet(HTML) 90 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL