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OR2C04A Datasheet(PDF) 30 Page - List of Unclassifed Manufacturers |
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OR2C04A Datasheet(HTML) 30 Page - List of Unclassifed Manufacturers |
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30 / 192 page  Data Sheet ORCA Series 2 FPGAs June 1999 30 Lucent Technologies Inc. Programmable Input/Output Cells (continued) 5-2843(F).r8 Figure 26. PIC Architecture DT DT DT DT PA PB PC PD PXL[1] PXL[0] PX2[2] PX2[3] PX2[0] PX2[1] PX1[0] PX1[1] PX1[2] PX1[3] PXH[1] PXH[2] PXH[3] PXH[0] B A C D FE G Q PXL[0] PXL[1] PX2[0] PX2[1] PX2[2] PX2[3] PX1[0] PX1[1] PX1[2] PX1[3] PXH[1] PXH[2] PXH[3] PXH[0] B A C D PIC DETAIL F O N O LLDRV M I L J K N D C P Q M P P PLC-PIC Routing Resources There is no direct connection between the inter-PIC lines and the PLC lines. All connections to/from the PLC must be done through the connecting lines which are perpendicular to the lines in the PIC. The use of perpendicular and parallel lines will be clearer if the PLC and PIC architectures (Figure 23 and Figure 26) are placed side by side. Twenty-nine lines in the PLC can be connected to the 15 lines in the PIC. Multiple connections between the PIC PX1 lines and the PLC X1 lines are available. These allow buses placed in any arbitrary order on the I/O pads to be unscrambled when placed on the PLC X1 lines. Con- nections are also available between the PIC PX2 lines and the PLC X1 lines. There are eight tridirectional (four TRIDI/four TRIDIH) buffers in each PIC; they can do the following: s Drive a signal from an I/O pad onto one of the adja- cent PLC’s XL or XH lines s Drive a signal from an I/O pad onto one of the two PXL or four PXH lines in the PIC s Drive a signal from the PLC XL or XH lines onto one of the two PXL or four PXH lines in the PIC s Drive a signal from the PIC PXL or PXH lines onto one of the PLC XL or XH lines |
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