OR2C04A datasheet(56/192 Pages) ETC

56 / 192 page

Data Sheet

ORCA Series 2 FPGAs

June 1999

Lucent Technologies Inc.

Special Function Blocks (continued)

There are four

ORCA-defined instructions. The PLC

scan rings 1 and 2 (PSR1, PSR2) allow user-defined

internal scan paths using the PLC latches/FFs. The

RAM_Write Enable (RAM_W) instruction allows the

user to serially configure the FPGA through TDI. The

RAM_Read Enable (RAM_R) allows the user to read

back RAM contents on TDO after configuration.

ORCA Boundary-Scan Circuitry

The

ORCA Series boundary-scan circuitry includes a

test access port controller (TAPC), instruction register

(IR), boundary-scan register (BSR), and bypass regis-

ter. It also includes circuitry to support the four pre-

defined instructions.

Figure 49 shows a functional diagram of the boundary-

scan circuitry that is implemented in the

ORCA series.

The input pins’ (TMS, TCK, and TDI) locations vary

depending on the part, and the output pin is the dedi-

cated TDO/RD_DATA output pad. Test data in (TDI) is

the serial input data. Test mode select (TMS) controls

the boundary-scan test access port controller (TAPC).

Test clock (TCK) is the test clock on the board.

The BSR is a series connection of boundary-scan cells

(BSCs) around the periphery of the IC. Each I/O pad on

the FPGA, except for CCLK, DONE, and the boundary-

scan pins (TCK, TDI, TMS, and TDO), is included in

the BSR. The first BSC in the BSR (connected to TDI)

is located in the first PIC I/O pad on the left of the top

side of the FPGA (PTA PIC). The BSR proceeds clock-

wise around the top, right, bottom, and left sides of the

array. The last BSC in the BSR (connected to TDO) is

located on the top of the left side of the array (PLA3).

The bypass instruction uses a single FF which resyn-

chronizes test data that is not part of the current scan

operation. In a bypass instruction, test data received on

TDI is shifted out of the bypass register to TDO. Since

the BSR (which requires a two FF delay for each pad)

is bypassed, test throughput is increased when devices

that are not part of a test operation are bypassed.

The boundary-scan logic is enabled before and during

configuration. After configuration, a configuration

option determines whether or not boundary-scan logic

is used.

The 32-bit boundary-scan identification register con-

tains the manufacturer’s ID number, unique part num-

ber, and version, but is not implemented in the

ORCA

series of FPGAs. If boundary scan is not used, TMS,

TDI, and TCK become user I/Os, and TDO is 3-stated

or used in the readback operation.

5-2840(C).r7

Figure 49.

ORCA Series Boundary-Scan Circuitry Functional Diagram

TAP

CONTROLLER

BOUNDARY-SCAN REGISTER

PSR2 REGISTER (PLCs)

BYPASS REGISTER

DATA

MUX

INSTRUCTION DECODER

INSTRUCTION REGISTER

RESET

CLOCK-IR

SHIFT-IR

UPDATE-IR

PUR

TDO

SELECT

ENABLE

RESET

CLOCK-DR

SHIFT-DR

UPDATE-DR

TDI

DATA REGISTERS

PSR1 REGISTER (PLCs)

CONFIGURATION REGISTER

(RAM_R, RAM_W)

I/O BUFFERS

VDD

TMS

VDD

TCK

VDD

PRGM

VDD

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