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OR2C04A Datasheet(PDF) 96 Page - List of Unclassifed Manufacturers |
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OR2C04A Datasheet(HTML) 96 Page - List of Unclassifed Manufacturers |
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96 / 192 page  Data Sheet ORCA Series 2 FPGAs June 1999 96 Lucent Technologies Inc. E19 PR2B PR3B PR3B PR4B PR5B I/O D20 PR2C PR3C PR3C PR4D PR5D I/O E18 PR2D PR3D PR3D PR3A PR4A I/O-VDD5 D19 PR1A PR2A PR2A PR2A PR3A I/O-WR C20 PR1B PR2B PR2B PR2B PR3B I/O E17 PR1C PR2C PR2C PR2C PR2A I/O D18 PR1D PR2D PR2D PR2D PR2D I/O C19 — PR1A PR1A PR1A PR1A I/O B20 — PR1B PR1B PR1B PR1B I/O C18 — PR1C PR1C PR1C PR1C I/O B19 — PR1D PR1D PR1D PR1D I/O A20 RD_CFGN RD_CFGN RD_CFGN RD_CFGN RD_CFGN RD_CFGN A19 — PT14D PT16D PT18D PT20D I/O B18 PT12D PT14C PT16C PT18C PT20C I/O B17 PT12C PT14B PT16B PT18B PT20A I/O C17 PT12B PT14A PT16A PT18A PT19D I/O D16 PT12A PT13D PT15D PT17D PT19A I/O-RDY/RCLK A18 — PT13C PT15C PT17A PT18A I/O A17 PT11D PT13B PT15B PT16D PT17D I/O C16 PT11C PT13A PT15A PT16C PT17C I/O B16 PT11B PT12D PT14D PT16A PT17A I/O A16 PT11A PT12C PT13D PT15D PT16D I/O-D7 C15 — PT12B PT13C PT15A PT16A I/O D14 PT10D PT12A PT13B PT14D PT15D I/O-VDD5 B15 PT10C PT11D PT13A PT14A PT15A I/O A15 PT10B PT11C PT12D PT13D PT14D I/O C14 PT10A PT11B PT12B PT13B PT14B I/O-D6 B14 PT9D PT11A PT12A PT13A PT14A I/O A14 PT9C PT10D PT11D PT12D PT13D I/O C13 — PT10C PT11C PT12C PT13C I/O B13 PT9B PT10B PT11B PT12B PT13B I/O A13 PT9A PT10A PT11A PT12A PT13A I/O-D5 D12 PT8D PT9D PT10D PT11D PT12D I/O C12 PT8C PT9C PT10C PT11C PT12C I/O B12 PT8B PT9B PT10B PT11B PT12B I/O A12 PT8A PT9A PT10A PT11A PT12A I/O-D4 B11 PT7D PT8D PT9D PT10D PT11D I/O C11 PT7C PT8C PT9C PT10C PT11C I/O A11 PT7B PT8B PT9B PT10B PT11B I/O A10 PT7A PT8A PT9A PT10A PT11A I/O-D3 Pin Information (continued) Table 25. OR2C/2T06A, OR2C/2T08A, OR2C/2T10A, OR2C/2T12A, and OR2C/2T15A/B 256-Pin PBGA Pinout (continued) Pin 2C/2T06A Pad 2C/2T08A Pad 2C/2T10A Pad 2C/2T12A Pad 2C/2T15A/B Pad Function Notes: The W3 pin on the 256-pin PBGA package is unconnected for all devices listed in this table. The OR2C/2T08A do not have bond pads connected to the 256-pin PBGA package pins F2 and Y17. The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series. The pins labeled VSS-ETC are the 4 x 4 array of thermal balls located at the center of the package. The balls can be attached to the ground plane of the board for enhanced thermal capability (see Table 29), or they can be left unconnected. |
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