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OR2C04A Datasheet(PDF) 36 Page - List of Unclassifed Manufacturers

Part # OR2C04A
Description  Field-Programmable Gate Arrays
PDF  192 Pages
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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OR2C04A Datasheet(HTML) 36 Page - List of Unclassifed Manufacturers

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Data Sheet
ORCA Series 2 FPGAs
June 1999
36
Lucent Technologies Inc.
Interquad Routing (continued)
PIC Interquad (MID) Routing
Between the PICs in each quadrant, there is also con-
nectivity between the PIC routing and the interquad
routing. These blocks are called LMID (left), TMID
(top), RMID (right), and BMID (bottom). The TMID rout-
ing is shown in Figure 33. As with the hIQ and vIQ
blocks, the only connectivity to the PIC routing is to the
global PXH and PXL lines.
The PXH lines from the one quadrant can be con-
nected through a CIP to its counterpart in the opposite
quadrant, providing a path that spans the array of PICs.
Since a passive CIP is used to connect the two PXH
lines, a 3-state signal can be routed on the two PXH
lines in the opposite quadrants, and then connected
through this CIP. As with the hIQ and vIQ blocks, CIPs
and buffers allow nibble-wide connections between the
interquad lines, the XH lines, and the XL lines.
5-4201(F).r4
Figure 33. Top (TMID) Routing
PXL[1]
PXL[0]
PX4[3]
PX4[2]
PX4[1]
PX4[0]
PX1[3]
PX1[2]
PX1[1]
PX1[0]
PXH[2]
PXH[1]
PXH[0]
HX4[3]
HX4[2]
HX4[1]
HX4[0]
PXH[3]
PXL[1]
PXL[0]
PX4[3]
PX4[2]
PX4[1]
PX4[0]
PX1[3]
PX1[2]
PX1[1]
PX1[0]
PXH[2]
PXH[1]
PXH[0]
HX4[3]
HX4[2]
HX4[1]
HX4[0]
PXH[3]



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