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OR2C04A Datasheet(PDF) 111 Page - List of Unclassifed Manufacturers |
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OR2C04A Datasheet(HTML) 111 Page - List of Unclassifed Manufacturers |
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111 / 192 page  Data Sheet June 1999 ORCA Series 2 FPGAs Lucent Technologies Inc. 111 N24 PR7A PR8A PR9A PR11A VDD5 I/O-VDD5 M26 PR7B PR8B PR9B PR11D PR14D I/O L25 PR7C PR8C PR9C PR10A PR13A I/O M24 PR7D PR8D PR9D PR10D PR13D I/O L26 PR6A PR7A PR8A PR9A PR12A I/O-CS1 M23 PR6B PR7B PR8B PR9D PR12D I/O K25 PR6C PR7C PR8C PR8A PR11A I/O L24 PR6D PR7D PR8D PR8D PR11D I/O K26 PR5A PR6A PR7A PR7A PR10A I/O-CS0 K23 PR5B PR6B PR7B PR7B PR10B I/O J25 PR5C PR6C PR7C PR7C PR10C I/O K24 PR5D PR6D PR7D PR7D PR10D I/O J26 PR4A PR5A PR6A PR6A PR9A I/O H25 PR4B PR5B PR6B PR6B PR9B I/O H26 PR4C PR5C PR6C PR6C PR9C I/O J24 PR4D PR5D PR6D PR6D PR9D I/O G25 PR3A PR4A PR5A PR5A PR8A I/O-RD H23 PR3B PR4B PR5B PR5B PR7A I/O G26 — PR4C PR5C PR5C PR7C I/O H24 PR3C PR4D PR5D PR5D PR6A I/O F25 PR3D PR3A PR4A PR4A VDD5 I/O-VDD5 G23 — PR3B PR4B PR4B PR5B I/O F26 — PR3C PR4C PR4C PR5C I/O G24 — PR3D PR4D PR4D PR5D I/O E25 PR2A PR2A PR3A PR3A PR4A I/O-WR E26 PR2B PR2B PR3B PR3B PR4B I/O F24 — — PR3D PR3D PR4D I/O D25 PR2C PR2C PR2A PR2A PR3A I/O E23 PR2D PR2D PR2D PR2D PR3D I/O D26 PR1A PR1A PR1A PR1A PR2A I/O E24 PR1B PR1B PR1B PR1B PR2D I/O C25 PR1C PR1C PR1C PR1C PR1A I/O D24 PR1D PR1D PR1D PR1D PR1D I/O C26 RD_CFGN RD_CFGN RD_CFGN RD_CFGN RD_CFGN RD_CFGN A25 PT16D PT18D PT20D PT24D PT30D I/O B24 PT16C PT18C PT20C PT24C PT30A I/O A24 — — PT20B PT24B PT29B I/O B23 PT16B PT18B PT20A PT24A PT29A I/O C23 PT16A PT18A PT19D PT23D PT28D I/O Pin Information (continued) Table 27. OR2C/2T10A, OR2C/2T12A, OR2C/2T15A/B, OR2C/2T26A, and OR2T40A/B 352-Pin PBGA Pinout (continued) Pin 2C/2T10A Pad 2C/2T12A Pad 2C/2T15A/B Pad 2C/2T26A Pad OR2T40A/B Pad Function Notes: The pins labeled I/O-VDD5 are user I/Os for the OR2CxxA and OR2TxxB series, but they are connected to VDD5 for the OR2TxxA series. The pins labeled VSS-ETC are the 6 x 6 array of thermal balls located at the center of the package. The balls can be attached to the ground plane of the board for enhanced thermal capability (see Table 29), or they can be left unconnected. |
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