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HT85F2270 Datasheet(PDF) 62 Page - Holtek Semiconductor Inc

Part # HT85F2270
Description  Standard 8051 8-Bit Flash MCU
PDF  226 Pages
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Manufacturer  HOLTEK [Holtek Semiconductor Inc]
Direct Link  http://www.holtek.com
Logo HOLTEK - Holtek Semiconductor Inc

HT85F2270 Datasheet(HTML) 62 Page - Holtek Semiconductor Inc

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Standard 8051 8-Bit Flash MCU
HT85F2260/HT85F2270/HT85F2280
The main system clock source, known as fSYS, and which is used by the CPU and the peripheral
functions, can come from one of three sources. These are the internal HIRC oscillator, the external
crystal HXT oscillator or a frequency multiplied version of these oscillators using the internal
PLL. The selection is implemented using the SCKS0 and SCKS1 bits in the SCCR register. The
HXT and HIRC oscillators also have independent enable control bits, which are the HXTEN and
HIRCEN bits in the HSOCR register. There are also two oscillator status bits, HIRCRDY and
HXTRDY, in the HSOCR register to indicate whether the oscillators are ready for operation. After
power on, these bits should be monitored by the program to indicate the “ready or not” status of the
respective oscillator, before they are used with instruction execution. After power on, the device
will automatically select the HIRC oscillator as its default system clock, which can be changed later
by the application program.
There are two additional internal 32kHz low frequency clocks for the peripheral circuits. These are
the external crystal LXT oscillator and the internal LIRC oscillators. The selection is implemented
using the LSOSEL bit in the LSOCR register. There is a low frequency oscillator status bit,
LSORDY, to indicate the “ready or not” status of the low frequency oscillator. This bit is common
to both low frequency oscillators, and should be monitored by the program to indicate the “ready or
not” status of the oscillator before it is used for instruction execution. This bit will be automatically
cleared to zero during low speed oscillator switching and set high once the chosen oscillator is stable.
System Clock Control Register – SCCR
SFR Address: ECh
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
SCKS1
SCKS0
R/W
—
—
—
—
—
—
R/W
R/W
POR
—
—
—
—
—
—
0
0
Bit 7~2
Unimplemented, read as “0”
Bit 1~0
SCKS1, SCKS0: High Frequency System clock select
00: HIRC oscillator clock source
01: HIRC oscillator clock source
10: HXT oscillator clock source
11: PLL clock source
The HIRC will be the default system clock source after a power on reset.
When switching between different clock sources an oscillator stabilisation time delay
must be provided before continuing with program execution.



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