HT85F2270 datasheet(96/226 Pages) HOLTEK

96 / 226 page

Rev. 1.00

96 of ��6

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Standard 8051 8-Bit Flash MCU

HT85F2260/HT85F2270/HT85F2280

IRCON Register

SFR Address: C0h

Bit

Name

EXF�

TF�

IEX6

IEX�

IEX4

IEX�

—

R/W

—

POR

—

Bit 7

EXF2: Timer 2 external reload interrupt request flag

0: No request

1: Interrupt request

The EXF2 bit will be set high by a negative transition on the T2EX pin. This bit must

be cleared using the application program. The EXF2 bit will be invalid in the Timer 2

Timer/Counter mode.

Bit 6

TF2: Timer 2 overflow interrupt request flag

0: No request

1: Interrupt request

This bit must be cleared using the application program.

Bit 5

IEX6: External interrupt 6 interrupt request flag

0: No request

1: Interrupt request

This bit is triggered by rising edge of external interrupt INT6. The IEX6 flag also will

be set high when Timer 2 compare mode is enabled and counter value (TH2, TL2)

is equal to Compare/Capture register 3 (CCH3, CCL3). Once the program into the

interrupt subroutine, the IEX6 flag will be cleared by hardware automatically.

Bit 4

IEX5: External interrupt 5 interrupt request flag

0: No request

1: Interrupt request

This bit is triggered by rising edge of external interrupt INT5. The IEX5 flag also will

be set high when Timer 2 compare mode is enabled and counter value (TH2, TL2)

is equal to Compare/Capture register 2 (CCH2, CCL2). Once the program into the

interrupt subroutine, the IEX5 flag will be cleared by hardware automatically.

Bit 3

IEX4: External interrupt 4 interrupt request flag

0: No request

1: Interrupt request

This bit is triggered by rising edge of external interrupt INT4. The IEX4 flag also will

be set high when Timer 2 compare mode is enabled and counter value (TH2, TL2)

is equal to Compare/Capture register 1 (CCH1, CCL1). Once the program into the

interrupt subroutine, the IEX4 flag will be cleared by hardware automatically.

Bit 2

IEX3: External interrupt 3 interrupt request flag

0: No request

1: Interrupt request

This bit is triggered by falling or rising edge of external interrupt INT3. The IEX3 flag

also will be set high when Timer 2 compare mode is enabled and counter value (TH2,

TL2) is equal to Compare/Reload/Capture register (CRCH, CRCL). Once the program

into the interrupt subroutine, the IEX3 flag will be cleared by hardware automatically.

Bit 1

IEX2: External interrupt 2 interrupt request flag

0: No request

1: Interrupt request

This bit is triggered by falling or rising edge of external interrupt INT2. This bit will be

cleared by hardware automatically.

Bit 0

Unimplemented, read as "0"

HT85F2270 Datasheet(PDF) 96 Page - Holtek Semiconductor Inc

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