HT85F2270 datasheet(64/226 Pages) HOLTEK

64 / 226 page

Rev. 1.00

64 of ��6

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Standard 8051 8-Bit Flash MCU

HT85F2260/HT85F2270/HT85F2280

Phase Locked Loop – PLL

All devices contain a fully internal PLL function which is used to multiply the frequency of the

selected high speed oscillator, either HIRC or HXT. As all PLL functions are internal, no external

components, including those for the loop filter, are required.

The PLL is enabled by the PLLEN bit in the PLLCR register. After being enabled the PLL must

be given a certain amount of time to lock and stabilise. After the PLL is enabled the PLLRDY bit

should be monitored to indicate when the PLL has locked and is ready for use. If the PLL function

is disabled, then the high frequency oscillators can be used directly as the system clock. The PLL

input clock source, from either the HIRC or HXT oscillators, is determined by the PLLSRC bit in

the PLLCR register. The frequency multiplier range has a range of one to eight times, selected by

the PLLM0~PLLM2 bits in the PLLCR register.

Changing the PLL Frequency

After the PLL is enabled and is being used as the system clock, its frequency can be changed

dynamically by the application program, by programming the PLLM0~PLLM2 bits in the PLLCR

frequency switching. There are a total of eight different PLL frequency multiplier selections,

however during dynamic PLL frequency changing, the multiplier value should only be changed

one stage at a time. In addition a recommended delay of at least 10 instruction cycles, which can

be implemented by 10 NOP instructions, should be inserted after each frequency multiplier stage

change to allow the PLL to re-lock and stabilise. Note that the PLLRDY bit will remain at a high

level during any dynamic PLL frequency change and cannot be used to indicate PLL stability after

the PLL changes frequency. The accompanying flowchart illustrates this point.

Example: Change the system clock from 8 MHz to 16 MHz

PLLCR register

PLLM 2:0 bits=001

PLLCR register

PLLM 2:0 bits=010

NOP × 10

fSYS=8MHz

NOP × 10

PLLCR register

PLLM 2:0 bits=011

Delay to allow PLL to lock

fSYS=12MHz

Delay

fSYS=16MHz

Delay

16MHz system clock now ready for use

Note: 4�Hz HXT external cr�stal oscillator

PLL Frequency Changing

HT85F2270 Datasheet(PDF) 64 Page - Holtek Semiconductor Inc

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