IMX53IEC datasheet(28/173 Pages) FREESCALE

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i.MX53 Applications Processors for Industrial Products, Rev. 6

Freescale Semiconductor

Electrical Characteristics

4.3.2

LPDDR2 I/O DC Parameters

The LPDDR2 I/O pads support DDR2/LVDDR2, LPDDR2, and DDR3 operational modes.

4.3.2.1

DDR2 Mode I/O DC Parameters

The DDR2 interface fully complies with JESD79-2E DDR2 JEDEC standard release April, 2008. The

parameters in Table 11 are guaranteed per the operating ranges in Table 6, unless otherwise noted.

Input current (100 k

Ω Pull-down)

Iin

Vin = 0 V

Vin = OVDD

——

μA

Keeper Circuit Resistance

—

1304

—k

1 Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6 V,

and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/ undershoot must

be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other

methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device.

2 To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC

level through to the target DC level, VIL or VIH. Monotonic input transition time is from 0.1 ns to 1 s.

3 Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.

4 Use an off-chip pull resistor of less than 60 kΩ to override this keeper.

Table 11. DDR2 I/O DC Electrical Parameters1

1 Note that the JEDEC SSTL_18 specification (JESD8-15a) for a SSTL interface for class II operation supersedes any

specification in this document.

Parameters

Symbol

Test Conditions

Min

Typ

Max

Unit

High-level output voltage2

2 OVDD is the I/O power supply (1.7 V–1.9 V for DDR2)

Voh

Ioh = -0.1 mA

0.9 x OVDD

—

Low-level output voltage

Vol

Iol = 0.1 mA

—

0.1 x OVDD

Input Reference Voltage

Vref

0.49 x OVDD 0.5 x OVDD

0.51 x OVDD

DC input High Voltage (data pins)

Vihd

(dc)

—

Vref+0.125V

—

OVDD+0.3

DC input Low Voltage (data pins)

Vild (dc)

—

-0.3

—

Vref - 0.125V

DC Input voltage range of each

differential input3

3 Vin(dc) specifies the allowable DC voltage exertion of each differential input.

Vin (dc)

—

-0.3

—

OVDD + 0.3

DC Differential input voltage required for

switching 4

Vid (dc)

—

0.25

—

OVDD + 0.6

Termination Voltage

Vtt

Vref - 0.04

Vref

Vref + 0.04

Input current (no pull-up/down)

Iin

Vin = 0 V

Vin = OVDD

—

μA

Keeper Circuit Resistance

—

1305

—k

Table 10. GPIO I/O DC Electrical Characteristics (continued)

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

IMX53IEC Datasheet(PDF) 28 Page - Freescale Semiconductor, Inc

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