IMX53IEC datasheet(64/173 Pages) FREESCALE

64 / 173 page

i.MX53 Applications Processors for Industrial Products, Rev. 6

Freescale Semiconductor

Electrical Characteristics

Figure 31 and Table 43 show the data read timing parameters.

Figure 31. DDR SDRAM DQ vs. DQS and SDCLK Read Cycle

Table 42. DDR SDRAM Write Cycle 1 2 3

1 All timings are refer to Vref level cross point.

Reference load model is 25

Ω resistor from each of the DDR outputs to VDD_REF.

3 To receive the reported setup and hold values, write calibration should be performed in order to locate the DQS in the middle

of DQ window.

Parameter

Symbol

SDCLK = 400 MHz

Unit

Min

Max

DDR17

DQ and DQM setup time to DQS (differential strobe)

tDS

0.285

—

DDR18

DQ and DQM hold time to DQS (differential strobe)

tDH

0.285

—

DDR21

DQS latching rising transitions to associated clock edges

tDQSS

-0.25

+0.25

tCK

DDR22

DQS high level width

tDQSH

0.45

0.55

tCK

DDR23

DQS low level width

tDQSL

0.45

0.55

tCK

Table 43. DDR SDRAM Read Cycle 1

1 To receive the reported setup and hold values, read calibration should be performed in order to locate the DQS in the middle

of DQ window.

Parameter

Symbol

SDCLK = 400 MHz

Unit

Min

Max

DDR26

Minimum required DQ valid window width

except from LPDDR2

—0.6

—

DDR26(LP

DDR2)

Minimum required DQ valid window width

for LPDDR2

—0.425

—

DDR27

DQS to DQ valid data

—

0.275

0.475

SDCLK

SDCLK_B

DQS (input)

DQ (input)

DATA

DDR26

DDR27

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