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IMX53IEC Datasheet(PDF) 91 Page - Freescale Semiconductor, Inc

Part # IMX53IEC
Description  i.MX53 Applications Processors for Industrial Products
PDF  173 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

IMX53IEC Datasheet(HTML) 91 Page - Freescale Semiconductor, Inc

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Electrical Characteristics
i.MX53 Applications Processors for Industrial Products, Rev. 6
Freescale Semiconductor
91
The maximal accuracy of UP/DOWN edge of IPP_DATA is:
The DISP_CLK_PERIOD, DI_CLK_PERIOD parameters are programmed through the registers.
Figure 50 depicts the synchronous display interface timing for access level. The DISP_CLK_DOWN and
DISP_CLK_UP parameters are set through the Register. Table 61 lists the synchronous display interface
timing characteristics.
Figure 50. Synchronous Display Interface Timing Diagram—Access Level
Table 61. Synchronous Display Interface Timing Characteristics (Access Level)
ID
Parameter
Symbol
Min
Typ1
1The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display.
These conditions may be chip specific.
Max
Unit
IP16
Display interface clock
low time
Tckl
Tdicd-Tdicu-1.24
Tdicd2-Tdicu3
Tdicd-Tdicu+1.24
ns
IP17
Display interface clock
high time
Tckh
Tdicp-Tdicd+Tdicu-1.24
Tdicp-Tdicd+Tdicu
Tdicp-Tdicd+Tdicu+1.2
ns
IP18
Data setup time
Tdsu
Tdicd-1.24
Tdicu
—
ns
IP19
Data holdup time
Tdhd
Tdicp-Tdicd-1.24
Tdicp-Tdicu
—
ns
IP20o
Control signals offset
times (defines for each
pin)
Tocsu
Tocsu-1.24
Tocsu
Tocsu+1.24
ns
IP20
Control signals setup
time to display
interface clock
(defines for each pin)
Tcsu
Tdicd-1.24-Tocsu%Tdicp
Tdicu
—
ns
Accuracy
T
diclk
0.62ns
±
=
IP19
IP18
IP20
VSYNC
IP17
IP16
DRDY
HSYNC
other controls
IP20o
local start point
Tdicd
Tdicu
IPP_DISP_CLK
IPP_DATA



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