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IMX53IEC Datasheet(PDF) 99 Page - Freescale Semiconductor, Inc |
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IMX53IEC Datasheet(HTML) 99 Page - Freescale Semiconductor, Inc |
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99 / 173 page ![]() Electrical Characteristics i.MX53 Applications Processors for Industrial Products, Rev. 6 Freescale Semiconductor 99 Figure 55. Asynchronous Parallel System 68k Interface (Type 2) Timing Diagram Display operation can be performed with IPP_WAIT signal. The DI reacts to the incoming IPP_WAIT signal with 2 DI_CLK delay. The DI finishes a current access and a next access is postponed until IPP_WAIT release. Figure 56 shows timing of the parallel interface with IPP_WAIT control. RS WR RD RS WR RD (READ/WRITE) (ENABLE) (READ/WRITE) (ENABLE) Burst access mode with sampling by ENABLE signal Single access mode (all control signals are not active for one display interface clock after each display access) IPP_CS IPP_DATA IPP_CS IPP_DATA |
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