IMX53IEC datasheet(69/173 Pages) FREESCALE

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Electrical Characteristics

i.MX53 Applications Processors for Industrial Products, Rev. 6

Freescale Semiconductor

SCKT rising edge to FST out (wr) high6

—

20.0

10.0

x ck

i ck

SCKT rising edge to FST out (wr) low6

—

22.0

12.0

x ck

i ck

SCKT rising edge to FST out (wl) high

—

19.0

9.0

x ck

i ck

SCKT rising edge to FST out (wl) low

—

20.0

10.0

x ck

i ck

SCKT rising edge to data out enable from high

impedance

—

22.0

17.0

x ck

i ck

SCKT rising edge to data out valid

—

18.0

13.0

x ck

i ck

SCKT rising edge to data out high impedance 77

—

21.0

16.0

x ck

i ck

FST input (bl, wr) setup time before SCKT falling edge6

—

2.0

18.0

—

x ck

i ck

FST input (wl) setup time before SCKT falling edge

—

2.0

18.0

—

x ck

i ck

FST input hold time after SCKT falling edge

—

4.0

5.0

—

x ck

i ck

HCKR/HCKT clock cycle

—

2 x TC

—

HCKT input rising edge to SCKT output

—

18.0

—

HCKR input rising edge to SCKR output

—

18.0

—

1 VCORE_VDD= 1.00 ± 0.10V

Tj = -40 °C to 125 °C

CL= 50 pF

2 i ck = internal clock

x ck = external clock

i ck a = internal clock, asynchronous mode

(asynchronous implies that SCKT and SCKR are two different clocks)

i ck s = internal clock, synchronous mode

(synchronous implies that SCKT and SCKR are the same clock)

3 bl = bit length

wl = word length

wr = word length relative

4 SCKT(SCKT pin) = transmit clock

SCKR(SCKR pin) = receive clock

FST(FST pin) = transmit frame sync

FSR(FSR pin) = receive frame sync

HCKT(HCKT pin) = transmit high frequency clock

HCKR(HCKR pin) = receive high frequency clock

5 For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register.

Table 48. Enhanced Serial Audio Interface (ESAI) Timing (continued)

No.

Characteristics1’2,3

Symbol

Expression3

Min

Max

Condition4 Unit

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