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10XSC425 Datasheet(PDF) 41 Page - Freescale Semiconductor, Inc |
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10XSC425 Datasheet(HTML) 41 Page - Freescale Semiconductor, Inc |
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41 / 56 page  Analog Integrated Circuit Device Data Freescale Semiconductor 41 10XSC425 Multiple messages can be transmitted in succession to accommodate those applications where daisy chaining is desirable, or to confirm transmitted data, as long as the messages are all multiples of 16 bits. Any attempt made to latch in a message that is not 16 bits will be ignored. The 10XSC425 has defined registers, which are used to configure the device and to control the state of the outputs. Table 11 summarizes the SI registers. Table 10. SI Message Bit Assignment Bit Sig SI Msg Bit Message Bit Description MSB D15 Watchdog in: toggled to satisfy watchdog requirements. D14 :D13 Register address bits used in some cases for output selection (Table 11). D12 :D10 Register address bits. D9 Not used (set to logic [0]). LSB D8:D0 Used to configure the inputs, outputs, and the device protection features and SO status content. Table 11. Serial Input Address and Configuration Bit Map SI Register SI Data D15 D1 4 D1 3 D1 2 D1 1 D1 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 STATR_s WDI N X X 0 0 0 0 0 0 0 0 SOA4 SOA3 SOA2 SOA1 SOA0 PWMR_s WDI N A1 A0 00 10 28W_s ON_s PWM6_s PWM5_s PWM4_s PWM3_s PWM2_s PWM1_s PWM0_s CONFR0 _s WDI N A1 A0 01 00 0 0 0 DIR_dis_ s SR1_s SR0_s DELAY2_s DELAY1_ s DELAY0_ s CONFR1 _s WDI N A1 A0 0 110 0 0 Retry_ unlimited_ s Retry_dis _s OS_dis_s OLON_dis _s OLOFF_di s_s OLLED_e n_s CSNS_rati o_s OCR_s WDI N A1 A0 1 000 Xenon _s BC1_s BC0_s OC1_s OC0_s OCHI_s OLCO1_s OLCO0_ s OC_mode _s GCR WDI N 0 0 1 010 VDD_ FAIL_ en PWM_e n CLOCK_s el TEMP_en CSNS_e n CSNS1 CSNS0 X OV_dis CALR WDI N 0 0 1 110 1 0 1 0 1 1 0 1 1 Register stateafter RSTB = 0 or VDD(FAIL) or VSUPPLY( POR) condition 00 0 X X X 0 0 0 0 0 0 0 0 0 0 x=Don’t care. s=Output selection with the bits A1A0 as defined in Table 12. |
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