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10XSC425 Datasheet(PDF) 47 Page - Freescale Semiconductor, Inc |
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10XSC425 Datasheet(HTML) 47 Page - Freescale Semiconductor, Inc |
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47 / 56 page  Analog Integrated Circuit Device Data Freescale Semiconductor 47 10XSC425 6.4.4 Serial Output Bit Assignment The 16 bits of serial output data depend on the previous serial input message, as explained in the following paragraphs. Table 23, summarizes SO returned data for bits OD15:OD0. • Bit OD15 is the MSB; it reflects the state of the Watchdog bit from the previously clocked-in message. • Bits OD14:OD10 reflect the state of the bits SOA4:SOA0 from the previously clocked-in message. • Bit OD9 is set to logic [1] in Normal mode (NM). • The contents of bits OD8:OD0 depend on bits D4:D0 from the most recent STATR command SOA4:SOA0 as explained in the paragraphs following Table 23. Table 23. Serial Output Bit Map Description Previous STATR SO Returned Data S O A 4 S O A 3 S O A 2 S O A 1 S O A 0 OD 15 OD 14 OD 13 OD 12 OD 11 OD 10 O D9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0 STATR _s A1 A0 0 0 0 WDI N SO A4 SOA 3 SOA 2 SO A1 SO A0 N M POR UV OV OLON _s OLOF F_s OS_s OT_s SC_s OC_s PWMR _s A1 A0 0 0 1 WDI N SO A4 SOA 3 SOA 2 SO A1 SO A0 N M 28W _s ON_ s PWM 6_s PWM 5_s PWM 4_s PWM3_s PWM2_s PWM1_s PWM0_s CONF R0_s A1 A0 0 1 0 WDI N SO A4 SOA 3 SOA 2 SO A1 SO A0 N M X X X DIR_d is_s SR1_ s SR0_s DELAY2_s DELAY1 _s DELAY0 _s CONF R1_s A1 A0 0 1 1 WDI N SO A4 SOA 3 SOA 2 SO A1 SO A0 N M X X Retry_ unlimit ed_s Retry_ dis_s OS_di s_s OLON_dis _s OLOFF_dis _s OLLED_ en_s CSNS_r atio_s OCR_s A1 A0 1 0 0 WDI N SO A4 SOA 3 SOA 2 SO A1 SO A0 N M Xeno n_s BC1 _s BC0_ s OC1_ s OC0_ s OCHI_s OCLO1_s OCLO0_ s OC_mod e_s GCR 0 0 1 0 1 WDI N SO A4 SOA 3 SOA 2 SO A1 SO A0 N M VDD _FAI L_e n PW M_e n CLOC K_sel TEMP _en CSNS _en CSNS1 CSNS0 X OV_dis DIAGR 0 0 0 1 1 1 WDI N SO A4 SOA 3 SOA 2 SO A1 SO A0 N M X X X X X X CLOCK_fail CAL_fail OTW DIAGR 1 0 1 1 1 1 WDI N SO A4 SOA 3 SOA 2 SO A1 SO A0 N M X X X X IN3 IN2 IN1 IN0 WD_en DIAGR 2 1 0 1 1 1 WDI N SO A4 SOA 3 SOA 2 SO A1 SO A0 N M X X X X X X0 1 1 Regist er state after RST= 0 or VDD(F AIL) or VSUPP LY(POR ) conditi on N/ A N/ A N/ A N/ A N/ A 0 0 0 0 0 0 0 X 0 0 0 0 00 0 0 s=Output selection with the bits A1A0 as defined in Table 12 |
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