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AN2783 Datasheet(PDF) 17 Page - STMicroelectronics

Part # AN2783
Description  PM8800 demonstration kit for standard and high power PoE
PDF  47 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

AN2783 Datasheet(HTML) 17 Page - STMicroelectronics

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AN2783
Input section
17/47
7
Input section
7.1
Diode bridges
Two diode bridges are required at the input because PD must be able to accept voltage from
an Ethernet cable with undefined polarity and coming from either Tx and Rx or spare pairs.
Diode bridges must be at least 0.5 A to 1 A, 100 V . They contribute to increasing the
resistance presented by the PD to the PSE during the signature phase. For this reason the
internal signature resistance is set to 24.5 k
Ω. Care must be taken to not exceed the
standard accepted values between 23.75 k
Ω and 26.25 kΩ.
On the high-power board the diode bridges are replaced with discrete Schottky diodes, that
due to the lower voltage drop, allow lower losses at high output power.
7.2
Input capacitors
The IEEE802.3af standard requires a capacitor whose values are between 50 nF to 120 nF
during the signature phase and a minimum of 5 µF during the operating phase. A 100 nF,
100 V ceramic capacitor is used, placed near the VIN pin of PM8800.
In order to reduce the conducted emission, a C-L-C input filter has been designed with a
100 V aluminum capacitor at the input side, a 3.3 µH inductor and three 100 V ceramic
capacitors on the output side.
The resonant frequency of the filter is:
Equation 1
It has been selected to be about 5-10 times above the control loop bandwidth, to not impact
the stability of the control loop.
Equation 2
7.3
Transient voltage suppression
The PD in some circumstances (ringing, overshoot transients, static electricity, ground
differences, etc.) can see hundreds or thousands of volts at its RJ45 input connector. The
energy associated with these voltages can be quite large.
A transient voltage suppressor (TVS) is typically applied at the input of the PD, after the
diode bridge, in parallel to the 100 nF input capacitor.
The TVS must absorb this energy, but the PD interface must be designed to withstand an
additional 20 V or 30 V above the operating range until the TVS limits the voltage.
The TVS must be selected with a standoff voltage higher than the maximum voltage of 57 V
defined in the PoE standard which means a clamping voltage that can easily reach 100 V.
Freq
1
2
π
LC
cer
⋅
⋅
()
----------------------------------------
=
C
cer
I
prms
8F
sw
∆V
ripple
⋅⋅
()
------------------------------------------------
≥



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